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I am a newbie in PCB design and I am presently working on my first PCB design which is a capacitive sensor.
I am drawing a 6 layered PCB and on the top layer I have all my components placed and routed completely.
On the bottom routing layer, I need to make use of a net that I connected in...
I am presently working on a PCB design for a sensor and I have just started learning Capture CIS and PCB Editor.
I completed the schematic in OrCAD Capture and cleared all my DRC errors. I have also succeeded in creating a netlist and thereby exporting it to PCB editor.
At this stage, I have a...
I am working on a project for the design of a capacitive sensor. In order to do that, I am required to compute capacitance using a simulation software like COMSOL. As I want to compare my simulation results with the theoretical results, I would like to know the formula to be used for the...
Can u help me debug errors in the fifo code?
I am trying to find error but I have not suceeded in finding any.
wr_in, //write_enable signal
rd_in, // read_enable
I have modified the code that I found on the net for my requirements.But, I realise that there are a few errors and I am unable to debug them.It would be great if you can help me with this.
my code and testbench are as follows:
I have designed a program for getting the output of a 8-bit fifo while taking the value fifo depth as 15 .Inorder to transmit my data, I need to wait for 15 bytes of information. Can u guide me as to how I should write a code for collecting 15 1 bytes of data till I get 15 bytes...
I have written a code for synchronous fifo and added a testbench as well. I have obtained the results but I am not able to understand the data out signal. I am not able to understand the meaning of the dout waveform.Kindly help me.
`timescale 10ns / 1ns
module fifo2 (wr...
HI, this is my code for synchronous fifo.I have tried to correct errors as much as possible but I have not suceeded. The error it says is illegal left hand assignment and shows many places.but I don`t know how to correct? Thanks for ur help.
`timescale 1ns / 1ps
module fifo2 (wr...
I need to design a clock divider as part of my verilog program for SPI but unfortunately I have a few errors and I am not able to correct the errors.
the code is as follows:
I have been assigned a project wherein I need to design a PCIe to Peripheral controller in OrCAD.As further information,I have been given a block diagram of the PCIe and nothing more. Can someone tell me how to get a headstart to this problem? Do I have to use OrCAD capture for...