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  1. D

    which verification methodology to be used??

    Yes. You can say that the methodology we select depends upon tool or vendor. If we use Synopsys VCS, we may have to choose VMM. If we go with Mentor, OVM is preferred.
  2. D

    What is a "callback" in Systemverilog?

    what is callback in systemverilog We may have to create a verification environment that can be used for all the tests. Test program should be able to inject new code without modifying original classes. Any change in the transaction(like injecting errors, inserting delays, synchronizing this...
  3. D

    which verification methodology to be used??

    Recent trend has System Verilog as verification language to increase the portability and reuse of TB features. For communication between various layers of TB, OVM methodology is preferred.
  4. D

    Data buffer for PCIe physical layer verification

    PCIe Phy Hi I am doing PCIe physical layer verification. For Gen1 and Gen2, PCIe transmits 20 bit data and receives 16 bit data. I am in the process of bulding up a test bench environment for this. I am actually preparing an expected data buffer. This is 16 bit buffer. Need to take 16 bits...
  5. D

    Looking for project that uses OCP-IP protocol

    Re: OCP-IP protocol We used Verilog for OCP models and USB OTG controller. Regards DTN
  6. D

    What does inter frame gap in ethernet contain?

    Re: ethernet For 10MBPS slot time is 512 bits, min Inter Packet Gap(IPG) is 9.6us & Min Frame size is 64 bytes For 100MBPS slot time is 512 bits, min Inter Packet Gap(IPG) is 0.96us & Min Frame size is 64 bytes For 1000MBPS slot time is 512 Bytes, min Inter Packet Gap(IPG) is 0.096us & Min...
  7. D

    Role of DMA in USB????

    The input and output devices and their drivers expect to be able to put/get data in response to a hardware interrupt from the DMA controller when their transducer has processed one service period of data. The DMA controller can move a single sample between the device and the host buffer at a...
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    Looking for project that uses OCP-IP protocol

    Re: OCP-IP protocol We used OCP as an interface for our USB OTG. You can get details about OCP from **broken link removed**
  9. D

    verification to design engg

    Verification to Design is easier. But and RTL guy trying to change to verification is a bit difficult. Time depends on ur competency.
  10. D

    gate level simulation issue

    Initialize all the inputs to proper value
  11. D

    What are the job requirements for a front-end ASIC engineer?

    Re: ASIC engg Basic things u need to know include 1. Basic Digital Electronics 2. Verilog/VHDL programming basics(Basic theory) 3. What is ASIC & FPGA ? 4. Tools used in full front end flow. But dont try to understand much about tools if u want to be in front end vlsi. But, if u want to be on...
  12. D

    Why we are using only D Flip-Flop in IC design?

    Re: D Flip-Flop D Flipflop is completely scannable(Controllable & Testable).
  13. D

    What's the best reference to learn System Verilog?

    Please let me know best source to learn System Verilog.
  14. D

    FAQ's on Ethernet,UART,USB

    U can download a free copy from IEEE site. Ethernet specs are freely available on net.
  15. D

    Looking for information about DFT Rules

    Re: DFT Rules Basic DFT rules include: ( I remember only these) 1. Clock & data should not change at same time. 2. No combinational loopbacks 3. Clock should not feed data input.
  16. D

    UTMI+L3 digital part verification

    Hi I am working on verification part of UTMI transceiver. RTL for digital part inside UTMI+L3 is developed and I am supposed to develop TB setup from the scratch. Please suggest a TB architecture for the same. Also, let me know what type of assertions are better to use in this scenario. Thank...
  17. D

    AMBA..........what is this.........?

    AMBA is intended to address the requirements of high performance designs. AMBA bus protocol is designed to be used with a central multiplexer interconnection scheme. AMBA AHB(Advanced High Performance Bus) is a new level of bus which sits above the APB(Advanced Peripheral Bus) and implements the...
  18. D

    FAQ's on Ethernet,UART,USB

    You need to know the protocol well for any interviews. It can be ethernet or usb, they deal with data transfer. For both the designs, one side there will be a standard bus interface(AHB/PCI/OCP ...etc). On the other side, both will have PHY layer . In ethernet the main part is transmission &...
  19. D

    What is the difference between test vectors ,cases & ben

    Re: regarding testbenches From rtl simulations point of view, test vectors & testcases hold same meaning. Testbench provides inputs to the design(RTL) and expects an output. For this operation( Testbench provide proper inputs to rtl and rtl responds in proper way), to happen, we need to...

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