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I use Automatic gated CTS, and it is recommended by my foundry to set maxsinktran and maxbuftran to 2ns. Also I've found that the required maxtran is 4ns by my library.
After running CTS, there are some max tran violations in the CTS report for some of my clocks. like below:
When I check the design in RTL compiler 10.1 after synthesis, I get the following summary for my design.
I know that Assigns are not good and should be removed before importing design in SoC encounter and I know how to do it.
But my question is about the Constant hierarchical...
Thanks Morris for your reply.
Yes, exactly. I have half a cycle set-up time
As far as I understood by reading the Encounter RTL compiler user manuals, setting the input delay is critical when we need to capture the data at the input at same clock edge which it was launched, so extra delay is...
I have a question about setting input and output delays in RTL compiler.
I know the definition of input and output delays and why it is necessary to set them in order to be able to interface with external devices.
However my question is this:
I know that in my front-end the...