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lock-in amplifier howto
I am designing a gilbert mixer for using in lock-in amplifier. The LO and RF freqency is same(10kHz) to generate a dc voltage to be measured, I think it is a simplest useage for a mixer, can any one tell me if I need to use PSS, PAC and Pnoise in cadence to simulate the...
I know the ESD protection is very important for chip safety, but the chip I will design is to sense very weak current(lest than pA), so the leakage of ESD protection circuit shoud be less than pA, do you know, normally, how much current is the leakage from ESD protection?
If it is larger than...
I just wonder if we must include ESD protection on every pad?
In the low noise and low leakage current application, the input pad should be away from ESD protection, is it right? But is it safe from ESD?
Does anyone know if the commercial opamp input has ESD protection?
I plan to design a low noise pmos buffer, which need large input and output swing rang, I have two topologies, can any one tell me which one is better? or any other topology is better than these two? Many thanks
1. I have a 5uA current already in my design, can I use 10X current mirror to bias...
I don't know how to do now, the Design kit uses dracula to erc and lvs, but doesn't support the post layout simulation if I use their opamp cells. is it strange?
And I think 10kHz is low, and the parasitic capacitor should be ok, is it right?
Can anyone help me?
Thanks a lot
I design an ic using an opamp cell from CDK, but the CDK can not do the post layout simulation including the opamp cell, my quetion is:
1. I don't want to design the opamp by myself, is there any problems for using the opamp cell from CDK?
2. what is the postlayout mainly for? I think it...