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  1. M

    Question on noise simulation in Cadence

    divide output noise by gain, you can get the input noise... the gain varies with frequency
  2. M

    Area for ESD protection diode

    calculate by leakage current and paracitic capacitor you can stand
  3. M

    how to simulate gilbert mixer in lock-in amplifier?

    lock-in amplifier howto I am designing a gilbert mixer for using in lock-in amplifier. The LO and RF freqency is same(10kHz) to generate a dc voltage to be measured, I think it is a simplest useage for a mixer, can any one tell me if I need to use PSS, PAC and Pnoise in cadence to simulate the...
  4. M

    Is ESD protection essential?

    I know the ESD protection is very important for chip safety, but the chip I will design is to sense very weak current(lest than pA), so the leakage of ESD protection circuit shoud be less than pA, do you know, normally, how much current is the leakage from ESD protection? If it is larger than...
  5. M

    Is ESD protection essential?

    I think the ESD leakage is in the range of pA, but not sure...
  6. M

    Is ESD protection essential?

    I just wonder if we must include ESD protection on every pad? In the low noise and low leakage current application, the input pad should be away from ESD protection, is it right? But is it safe from ESD? Does anyone know if the commercial opamp input has ESD protection? Many thanks Yong
  7. M

    about low noise pmos buffer design

    Do you mean I should choose the topology b? Can you please give me more explaination? Yes I will do the full layout. I have a 5uA current already in the layout. Thanks a lot.
  8. M

    about low noise pmos buffer design

    I plan to design a low noise pmos buffer, which need large input and output swing rang, I have two topologies, can any one tell me which one is better? or any other topology is better than these two? Many thanks 1. I have a 5uA current already in my design, can I use 10X current mirror to bias...
  9. M

    is post layout simulation obligatory?

    But I think the frequency is very low, 10KHz, so it is unnecessary to do the postlayout simulation, is it right?
  10. M

    lock in amplifier IC design

    ad630 lock in can anyone answeer it for me? thanks
  11. M

    is post layout simulation obligatory?

    I don't know how to do now, the Design kit uses dracula to erc and lvs, but doesn't support the post layout simulation if I use their opamp cells. is it strange? And I think 10kHz is low, and the parasitic capacitor should be ok, is it right? Can anyone help me? Thanks a lot
  12. M

    is post layout simulation obligatory?

    Hi, I design an ic using an opamp cell from CDK, but the CDK can not do the post layout simulation including the opamp cell, my quetion is: 1. I don't want to design the opamp by myself, is there any problems for using the opamp cell from CDK? 2. what is the postlayout mainly for? I think it...
  13. M

    lock in amplifier IC design

    lock in amplifier ic I plan to design a lock in amplifier IC to sense weak signal from noise, can anyone give me some advice or share some experience? I have no idea now. Many thanks Yong
  14. M

    How to design 1G ohm MOSFET resistor?

    How to realize it? is it difficult? how about the noise contribution of switched capacitor circuits
  15. M

    current mirror problem

    Yes, noise is an issue for me, then what should i do? just reduce w/l?
  16. M

    current mirror problem

    I have a 5 uA refference current, I need 200uA current by current mirror. can I use one current mirror with very large w/l (>100:1) to get this 200 uA current? Is there any problem? thanks a lot
  17. M

    How to design 1G ohm MOSFET resistor?

    1 g ohm resistor Europractice AMIS 0.7um I think technology is not important for the high MOSFET resistior, is it?
  18. M

    How to design 1G ohm MOSFET resistor?

    mosfet resistor I need to design a 1G ohm resistor on chip to dc bias a trans_C amplifier, I know I should use CMOS FET method, but how to realize it? Thanks advanced!
  19. M

    Input Current of CMOS Opamp

    It comes from leakage from gate oxide layer, very low, but exists!!
  20. M

    can matlab be used in the analog circuit simulation?

    matlab circuit simulator of course, matlab can do it. I remember I have seen a book for simulation circuits using matlab. but I think it is more complex to use matlab to simulate circuits

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