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  1. B

    How to create .lib file for my analog macro?

    When I finish analog layout and simulation, I'll want to create .lib to designer. Anyone can tell me which tools can do it. Thanks.
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    How to reduce power in back-end flow?

    I think multi-vdd should use difference voltage libraries to synthesis, right? Anyone can tell me how do it detailly? Or intraduce some papers. Thanks.
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    How to reduce power in back-end flow?

    Thank you sree205. But clock-gating and multi-Vt should be done by front-end engineer, what can back-end designer do? In addition, I not found the book, pls help me, thanks
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    How to reduce power in back-end flow?

    I'm a back-end engineer. Anyone can tell me how to reduce power in back-end flow? And some tools? Thanks.
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    help: how can I do in Astro follow with 0.13um process

    Thanks. I want to know Astro's follow with 0.13um process, pls help me. :D
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    help: how can I do in Astro follow with 0.13um process

    Any one can tell me there are what differences between 0.13um and 0.18um, when I run Astro. :DThanks.
  7. B

    Why is the timing-report difference between Astro and PT

    The timing is MET in Astro, but VIOLATE in PT. How can I do? Help me! Thanks!
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    Why is the timing-report difference between Astro and PT

    In one my case, timing check is met in Astro, but have violations in PT. Anyone can tell me why is the same instance's inc-time close to twice in PT's timint-report than Astro's ? :cry: How can I do to approach the timing-reportbetween Astro and PT? Thank you veryvery much!
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    Static Timing Analysis - two good STA presentations

    Static Timing Analysis Thanks , it's usefull .
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    different skew report between Astro and PrimeTime

    prime time report skew Thanks for your replies.
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    different skew report between Astro and PrimeTime

    astro skew report Hello eveybody,I have a difficulty: In one case, Astro's skew report is very good (0.2n). But We use SDF(from Astro) and SPEF(from Astro and StarRC) in PrimeTime, find the skew is very big (>0.8n), that so ATPG cannot pass. anyone can tell me why? I should how to do? Thanks :cry:
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    Why is the timing report difference between Astro and DC

    There are certainly different, path delay in dc just contains cell delay, and path delay in astro contains both cell delay and net delay Astro can ignore net delay.
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    Why is the timing report difference between Astro and DC

    In one case, I found the components of the timing path (same star point, same end point) is difference between Astro's timing-report and DC timing-report. Anyone can tell me why? Thanks
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    what is the diff between dual port & single port RAM?

    In our memory compiler I find one port , tow port, and dual port . I dont know what means.
  15. B

    What's the IC designer's future? Always designing or other?

    I am a new designer, I think my way is still long.
  16. B

    What exactly is done in floor planning and padding?

    floor planning floor planning = define chip size & place IO/PAD & place block is right?
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    Apollo II vs SE For Floorplanning & router - which one?

    Re: Astro & Soc encounter SoC encounter include Floorplan tools, Place and route, IPO tools, Cross talk tools, Power Grid analysis tools and others. Astro only P&R function. i heard Astro is a good tool for backend, it can do crosstalk. is it? :)

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