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Why cant we start a thread regarding verification using system verilog instead of multiple threads so that it is easy for anyone to follow rythem.
Here we can discuss all problems we are facing daily using sv and solutions for those.
I need some information regarding high speed usb . While the device in test mode, (if i set the device into transmit test packet ), what should be the test packet send by the device .
Could any one give the pattern of tets packet .(53 bytes of data ).
system verilog interview questions
Qi1)What is callback ?
(Qi2)What is factory pattern ?
(Qi3)Explain the difference between data types logic and reg and wire .
(Qi4)What is the need of clocking blocks ?
(Qi5)What are the ways to avoid race condition between testbench and RTL using...
i am inviting u all to discuss abt verification.
u can discuss here how to create verification environment, what stuff required to prove a good verification engineer,how to write bfms, etc.
u can post material here or books upload/download section or paste links...
what r the methods for improving the freequencey of a digital circuit .
i have listed here some methods .
4.combinational part optimization
if any other methods plz tell me .
Hi please post good veriog questions here .That can helpful to everyone to update
our knowledge dailybasis.
Here i am posting some questions today.
1. What is the use of "wait" statement in verilog.Where we can use this statement
in verilog program.
2. What is the difference...
if u post some good digital questions what ever u know ,that is helpful to
everyone update their knowledge day to date.
here i am posting some questions :
1.freequencey multiplication by two using combinational...
can ant one explain multi cycle paths and false paths very clearly ?
at what cases these paths will occur ?
what r the advantages and disadvantages ...
if anyone have material plz upload material ...