Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. M

    start discussion on verification using system verilog

    Guyz , Why cant we start a thread regarding verification using system verilog instead of multiple threads so that it is easy for anyone to follow rythem. Here we can discuss all problems we are facing daily using sv and solutions for those. regards Mallik
  2. M

    how to compile sysetem verilog file using cadence tools

    hi , How to complie a systemeverilog file and how to simulate using system verilog programme using cadence tools
  3. M

    Suggestion regarding USB2 or USB3 projects

    Hi, Anybody working on usb2 or usb3 please post ur doubts or suggestions . Sothat it could useful for many people whose working on usb . regards Mallik
  4. M

    anybody have the test packet of usb2.0

    Hi All, I need some information regarding high speed usb . While the device in test mode, (if i set the device into transmit test packet ), what should be the test packet send by the device . Could any one give the pattern of tets packet .(53 bytes of data ). regards Mallik
  5. M

    systemverilog interview questions post ur answers for these

    system verilog interview questions Qi1)What is callback ? (Qi2)What is factory pattern ? (Qi3)Explain the difference between data types logic and reg and wire . (Qi4)What is the need of clocking blocks ? (Qi5)What are the ways to avoid race condition between testbench and RTL using...
  6. M

    regarding modular inverse and modular reduction implementati

    Hi , Can u provide some documents for modular reduction and modular inverse regards mallik
  7. M

    abt modular exponetial ,inverse and multiplacation

    Hi how to implement the modular exponential ,modular inverse functions in verilog . or post some material regarding this. regards Mallik
  8. M

    regarding discussion abt verification

    hi , i am inviting u all to discuss abt verification. u can discuss here how to create verification environment, what stuff required to prove a good verification engineer,how to write bfms, etc. u can post material here or books upload/download section or paste links...
  9. M

    IRDA protocol specifications

    hi here i have attached irda protocol specification.
  10. M

    hi update (post ) ur projects here

    Hi all if u have any projects post here so that it can helpfull to others.
  11. M

    methods for improving freequencey

    hi what r the methods for improving the freequencey of a digital circuit . i have listed here some methods . 1. pipeling 2. parellism, 3.re timing 4.combinational part optimization if any other methods plz tell me . regards Mallik
  12. M

    what is "USE hold register & MUX architecture"

    hi to everyone, what is "USE hold register & MUX architecture" ? can any one explain clearly abt this one . regards mallikarjun
  13. M

    good verilog questions here

    Hi please post good veriog questions here .That can helpful to everyone to update our knowledge dailybasis. Here i am posting some questions today. 1. What is the use of "wait" statement in verilog.Where we can use this statement in verilog program. 2. What is the difference...
  14. M

    please post good digital questions here

    hi everyone, if u post some good digital questions what ever u know ,that is helpful to everyone update their knowledge day to date. here i am posting some questions : 1.freequencey multiplication by two using combinational...
  15. M

    regarding cycle based symulators and event based symulators

    hi every one , can anyone explain cycle based and event based symulators clearly.. regards mallikarjun
  16. M

    regarding multicycle and false paths

    hi everyone, can ant one explain multi cycle paths and false paths very clearly ? at what cases these paths will occur ? what r the advantages and disadvantages ... if anyone have material plz upload material ...
  17. M

    regarding source synchronous circuits

    hi everyone , can any one explain source synchronous circuits ? if anybody have material regarding this one please upload that one. it can great helpful for me. regards mallikarjun
  18. M

    regarding synchronous reset and asynchronous reset

    hi everyone, i have somuch confused about asynchronous reset and synchrounous reset. if anyone have material regarding this topic please upload this one. regards mallikarjun
  19. M

    Magma Low Power White Paper

    some useful files Hi here i have attached some useful files.
  20. M

    Explanation of abt bus functional model

    abt bus functional model hi anyone can explain abt bus functional model ? regards Mallikarjun

Part and Inventory Search