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  1. G

    Question on interfacing USB-OTG and USB

    Thank you! I guess I need to go though that 800 page doc sometime soon.... :sad:
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    Question on interfacing USB-OTG and USB

    Thank you, FvM. That means it is possible to make my custom board talk to USB 2.0 slave device "with" specific device class implemented in the OTG software? Is there any limitation on using OTG as a master vs. conventional USB master? Also, it would be great if you can point me to any...
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    Question on interfacing USB-OTG and USB

    Hello, I have a question on interfacing between USB-OTG device and USB 2.0 slave device. If I have a custom board with USB-OTG and a USB 2.0 compliant device, can I setup the custom board to be a master and make them communicate? Or, it is not allowed? Thanks, Gongdori
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    Newbie designed PCB crosstalk problem: 5MHz clk cross coupled to GND

    Out of curiosity, do you have one gnd plane for both digital and analog, or two split planes? How do you generate clock signal (in what standard) and how they are distributed? I'm not really an expert, but trying to understand why it happens...
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    Questions on Xilinx Virtex-4 power up requirements

    Hi all, In the Xilinx V4 datasheet, there is power supply ramp time requirement (Table 6 in DS595 DC and switching characteristics). It says that the three voltage rails should be ramp up within 0.2ms to 50 ms. (I assume 0V to the 100%?) I wonder where this requirement comes from. Is it...
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    [SOLVED] 1/10 th watt SMD resitor going bad after soldering is done

    I agree to Niri. You can get very different value by measuring it on the board.
  7. G

    Can anyone give me a reference on Cold sparing

    Hi all, I want to know more on "cold-sparing". Can anyone point me to any good reference please? Thanks! Gongdori

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