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I'm synthesizing a digital core using Synopsys DC, with a given clock, and I will later use this clock to drive the next blocks. Since the network will introduce a clock latency, I wanted a dedicated clock out port which outputs this delayed clock.
How do I go about it?
I tried to just to...
I'm designing a Delta Sigma modulator, and synthesizing it using SOC encounter. When I design the clock tree and choose the buffers and inverters to be used, Encounter always choose the largest buffer as the first stage, which shouldn't be. the later stages are smaller!. Is there a place...