# Search results

1. ### The strange structure of inductor of LC VCO

In order to tuning resonate frequency. I got it~ Thank you, Mazz!
2. ### The strange structure of inductor of LC VCO

lc-vco capacitor bank What's the 'green' structure in the picture. It has any advantage? Thank you!
3. ### Problem about the Verilog-A Simulation

There is something wrong with the spectre5141. After switch to spectre5033, the problem disappears.

5. ### Problem about the Verilog-A Simulation

I build a verilog-A model of PLL loop. And with spectre, to simulate the transient behavior. But after some time, about hundreds of us, the simulation is abruptly stopped. No warning or error information. What's wrong with my model or simulation setup? or spectre's bug?
6. ### About C code examples for circuit and system

Where are there some C code examples for circuits and systems? thank you!
7. ### Plz help me! There is some paper, which I forgot the name!

It talks about the difference of voltage controlled osc and current controlled osc. The phase noise of current controlled osc is better than the voltage controlled one. Could yuo tell me the paper title? Thank you!
8. ### Plz help me! There is some paper, which I forgot the name!

It talks about the difference of voltage controlled osc and current controlled osc. The phase noise of current controlled osc is better than the voltage controlled one. Could yuo tell me the paper title? Thank you!
9. ### Correction about the constant I/Q mismatch ?

OK Thank you!
10. ### Correction about the constant I/Q mismatch ?

Anyone can introduce some concept or paper, about the Correction on the constant I/Q mismatch ? Thank you!:D
11. ### Capacitance Multiplier will Introduce more Spur?

In the LF of PLL, if to use the capacitance multiplier in order to save area, it would introduce much more reference spur ?? Thank you!
12. ### How to reject the 3rd spur of upconversion mixer

Two different frequency clocks are mixed to a new clock. The IF (low frequency clock) signal can be degenerated to improve linearity. But the LO (high frequency clock) signal is very nonliear. It has 3rd and 5rd harmonic, which are mixed with the IF signal. Except the LC loading, RC filter...
13. ### Anyone could introduce something about two stage ring osc?

Anyone could introduce something about the two-stage ring oscillator? theory\paper\webpage, any other information. thank you
14. ### How to build a sin wave with only phase noise?

How to build a sin wave, that is with only phase noise, in the cadence? Thank you
15. ### A question about phase noise

There is an buffered oscillator. If the phase nosie of oscillator is -140dBc and the phase noise of buffer is -140dBc, the total phase noise is -134dBc? Thank you
16. ### How to do HRCX in use of assura

hrcx assura On the Extraction Tap of GUI, there is "Enable HRCX", and some cell name should be writed. But I don't know how to write it. And the document of assura don't give some example. Anyone could give some examples? Thank you
17. ### A question about the CMOS layout

i mean how many micron the distance of p-type could be away from another p-type? the distance is longer, the grounding is weaker, but the area is smaller
18. ### A question about the CMOS layout

How long do we need the p-type(on sub) or n-type(on n-well)? 5um? 10um? 20um? And under what kind of situation? 3ks
19. ### the series R of varactor is different between m=2 and f=2 ?

Re: the series R of varactor is different between m=2 and f=
20. ### the series R of varactor is different between m=2 and f=2 ?

Re: the series R of varactor is different between m=2 and f= from the simulation, the equivalent res of nmos varactor with M=2 F=1 is smaller than the one of with M=1 F=2. and, if the number of M*F is large, the difference of equivalent res is very obvious. so, could i say that the more...