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  1. C

    clock definitions and timing constraints...(dc - synopsys)

    create_clock -period 10.000000 -waveform {0.000000 5.000000} <Clock> Period speaks for istelf the two parameters in the waveform switch set the rising and falling edges, thereby setting the duty cycle and <clock> is substituted for your own signal name. SDC does not allow for any other...
  2. C

    clock definitions and timing constraints...(dc - synopsys)

    Do you mean: define_clock {Clock} -freq 100 -clockgroup default_clkgroup_0 -rise 0 -fall 5 -route 5 Which would be typical of the input constraint file for Synopsis (Scope source file) or create_clock -period 10.000000 -waveform {0.000000 5.000000} Clock which is a typical sdc file format -...
  3. C

    Actel modelsim D flip Flop simulation problem

    The answer to your question is yes - you must initialise the registers for Modelsim to behave correctly. The simplest thing to do is to provide a power-on reset or preset. As you are already using registers with preset why not assert pre at time zero then release the signal before the rest of...
  4. C

    Uart BFM -- (Bus function module)

    Some of these files may be useful as well - K
  5. C

    Uart BFM -- (Bus function module)

    Hi Karthik. Here is Actel's BFM for their coreapb_UART (bfm_apbslaveext.vhd) K

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