Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. N

    In cadence simulation how to introduce noise in current source?

    In cadence simulation i am trying to simulate a comparator. and i am using ideal current source (or measurement case off chip or external current). Now i want to simulate this comparator with current source having some noise so that i can verify the measurement case (external current source...
  2. N

    erroe while doing PEX using calibre in 65nm technology

    Dear All i have design a transconductance amplifier. done with layout of it.. cleared DRC and LVS and PEX. in PEX i m getting some warning. i m not able to understand those warning but because of these warning i m able to generate config view. i m attaching the error file
  3. N

    Cailbre PEX error with UMC65nm

    I am encountering the following error when I run extraction using Calibre v2011.4_14.13. Error while compiling rules file /Application/Cadence/CadencePDK/UMC65LLRF1P8M1T0F1U/RuleDecks/Calibre/G-DF-LOGIC/G-DF-LOGIC_MIXED_MODE65N-LL_LOW_K_CALIBRE-LVS-1.7-P1.txt: Error PEX5 on line 2302 of...
  4. N

    A fatal error in calibre PEX

    when i m running PEX using calibre i got fatal error. Rules file must contain a CAPACITANE ORDER statement. i m new in 65nm and i need to do layout of my circuit in 65nm. kindly help me.
  5. N

    [Moved]: LVS simulation in UMC 65nm technology using cadence

    hi i have simply design a inverter in 65nm and completed layout so that i can understand all layout process in 65nm. i have cleared DRC in LVS i have given the path of rules file. and for inputs i have given file path but i not able to give correct path for layout netlist so it is giving some...
  6. N

    IIP3 simulation of transconductance amplifier

    hi all plz let me know the test bench for IIP3 simulation of TCA(transconductance amplifier)
  7. N

    tranconductance amplifier

    hi i have design a transconductor amplifier with CMFB. i have used 250K resistance for resistive divider from analog lib. now i want to replace it with UMC component. maximum resistance in UMC65nmlib is 124K so connected two resistance in series. but TCA performance degraded alot. m i doing...
  8. N

    trans impedance amplifer

    hi i have designed a transimpedance amplifier having UGB 1GHZ and gain 60dB in AC analysis. but in transient analysis it is giving at output sin wave only upto 1.5MHz. after that frequency some sandom signal is coming why so?
  9. N

    mixer for front end receiver

    hi i have designed a passive mixer. for this individually i have tested TCA, TIA and switcing quard. all three are working fine individually. as i m trying to integrate its not working. so i reied one by one. now i got to know the problem. TIA is working upto only 2 MHZ. as i m putting any...
  10. N

    output voltage swing of two stage fully differential OPAMP

    i have designed two stage fully differential OPAMP. i have theoretically calculated output swing, it is coming 172mV to 945mV. power supply is 1.2V in 65nm technology. for checking in voltage swing in simulation i have connected it like a buffer and input sweeped fron 0 to vdd. but output is not...
  11. N

    query regarding two stage telescopic amplifier

    i m designing transimpedance amplifier... for high gain i have chosen telescopic structure. i have designed two stage cascode telescopic amplifier. it is working fine in open loop with common mode feedback. ac gain and traient both response are fine. but as i connecting RC feedback transient...
  12. N

    how to measure 1dB compression point of transimpedance amplifier

    hi i have designed transimpedance amplifier. but i have doubt in simulating 1 dB compression because in TIA input is current and output is voltage so is it correct to simulate 1dB-CP by using PSS analysis.
  13. N

    transimpedance amplifier

    hi i m working on front end receiver. so LNA, transconductance amplifier, passive mixer ans transimpedance amplifier blocks are needed. except transimpedance anplifier other blocks are almost ready..i have designed TIA as well. but i need very low input impedance TIA (in the range of 30-50ohm)...
  14. N

    linearity measurement using transient analysis

    hi can any1 tell how to do linearity measurement of an amplifier using transient analysis. i hv done it using PSS analysis. but somebody told me it can be done by transient analysis also. i did'nt understand exactly... hw it is possible. plz help me.
  15. N

    gilbert cell down conversion mixer

    can anybody tell in gilbert cell downconversion mixer RF bandwidth depends on what..... actually i want to design a downconversion mith RF BW 300M to 3G. at low frequency how should i tuned circuit.(300M to 1G). above 1 GHz it is Ok . i designed that
  16. N

    balun in cadence virtuoso

    does any one know what is the difference between balun and balun _ideal in RFlib of cadence virtuoso. thanks..
  17. N

    bandwidth plot of downconversion mixer using cadence

    hi i have designed a downconversion mixer, i hv measured conversion gain, noise figure, linearity but not able to measure bandwidth or freq range of mixer. i tried PSS + PSP but in this only IF freq i m able to sweep but did'nt get the option to sweep RF frequency. can any1 suggest me wat to do
  18. N

    reconfigurable downconversion mixer

    hi i have designed a reconfigurable switching downconversion gibert cell mixer with R and C load so that it can filter high frequency component. but at IF output it is not filtering high frequency component. but when i have designed simple downconversion mixer with RC load it was filtering...
  19. N

    reagarding design of transconductance amplifier

    i have designed a TCA in cadence in 65nm technoly, its bandwidth is around 3GHZ. when i have given ac input through capacitor and dc input through resistance it is not giving amplified output, even it is not giving the amplified sine wave which i have applied at input. but when i m giving direct...
  20. N

    CMOS differential buffer

    can any1 suggest some low frequency (around 50M -100Mhz) CMOS differential buffer.

Part and Inventory Search