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Groud Plane capacitance
I am designing a printed circuit board that has traces carrying TTL triggers from a national instrument timing board.
My question is : will it be a bad idea to put a ground plane in the secand layer. I was thinking the capacitance of the traces due to this ground plane...
I need a list of footprints available in layout plus standard libraries, so that i know which footprints i have and which ones i don't. I know how to make footprints myself but it would be waste of time to reinvent the wheel.
In the Users manual they keep refering to "OrCAD Layout...
high voltage pcb spacing
Let me tell you how i use the IPC-2221 to determine my clearance for 1 KV signal.
Lets use the B2 colum of the IPC table for the clearance for uncoated external conductor at sea level.
For 500 volts it has to be 98.4 mils. Now, for every additional volt we have to add...
high voltage spacing
The documents are helpful for my design. I can use the clearance numbers for my 1 KV potential difference between 2 traces uncoated. However, i want to calculate them analytically also, which is important if i have to jutify it to someone.
If i use 750 V/mils...
high voltage trace spacing
I am not sure i know what is surfance treaking? Can you please tell me more about it.
I have an RF voltage of +/- 215 volts. Also, i am making a board with soldermask on each side, which i guess give me a little advantage, i don't know why though...
high voltage pcb
I want to calculate analytically how much spacing is to be kept between the traces with high voltatge to prevent the arcing. Does any one has references of a text book or articles.
I have made a pcb and want to put a ground plane on the top layer. I created a copper pour obstacle and set it to attach to the ground net. My problem is the pins which are ground, connect to the plane with very thin traces approximately 10 mils. For example in the attached picture pin J2...