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But I still don't understand how to define the specification for the gate of 1X, 2X, 4X.... drive strength. For example with gate INV_X1 and INV_X2, what should be the W/L for them assuming with 65nm node?
Thank you so much.
I am designing standard cells and I believe that advice from standard cell designer expert will indeed helps me a lot. I have several doubts about define standard cell:
1. How can we define the input slew rates and output load capacitance for characterizing standard cell?
I am design a small circuit which include 2 module A and B. I want to do a process variation analysis manually with module A, and leave module B at typical corner. How can I let it work???
Currently, when setting to a process corner, both module A and B will be modeled by this...
I am a newbie with Mentor ADMS. I am trying to compile a simple tutorial from Mentor ADMS, adc-12. But there is an error in compiling as below:
Compiling file comparator.vhd
Compiling Entity Declaration comparator
Code generation for work.comparator
Compiling Architecture level0 of...
The problem I am facing is I got a post placement result from IC compiler. In each row, is it possible to shift a group of cells to the right or left and then insert a new cell in the new space??
Looking forward to your help
Thank you so much.
I am working on clock gating with DC compiler tool. The problem is when setting the minbitwidth with set_clock_gating_style command. Even though I set minimum bit width is 8, when evaluate the clock gating report, I discover that there are some gating cells connect to only 2 registers...