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    verilog code for designing a 16-bit alu by cascading 4 4-bit alu's

    hi all, we were given a project at college where we have to write a verilog code for cascading 4-bit alu's to form 16-bit alu's.we were comfortable in writing the code for 16 bit alu but it was suddenly changed to cascading of alu's .and my other question is whether to use case...

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