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I try to write the finite state verilog program that need to wait sometime in current state before go to next state. I used
example : repeat (10) @(posedge clk);
But error appear like this:
ERROR:Xst:850 - a.v line 32: Unsupported Event Control Statement.
Is there any other...
counter with 7474
I am facing sometime my counter is stuck at 0 during simple 3bits upcounter by using 7474 IC.
After I reconnect again. It is work. It is happen quite often. So I need to clearify myknowledge.
Normally I connect all PREset pins to VCC and all CLeaR pins to switch. When ever...
I just try to write a program which detect the 3x4 keypad and decode. I try to learn xilinx application xapp512__verilog.zip, but I still confuse how to write this program. Please show me links or examples (but please do not advise me to use google to search).
I am trying to learn verilog and downloading to xc9572 cpld during experiments. One suggests me I should use resistors at the input port, otherwise the port may damage. It is true or just over protecting.
I just try to study FSM.
I just wrote a FSM by using verilog. My plan is selling ticket with 15. user are allowed to add 5 or 10. whenever it reach to 15 ticket will come out and back to start state. If it reach to 20, ticket and change 5 and return to start state . It seem ok at this moment...
I hvae design very simple 2 bit up counter by using Xilinx schematic. I am using Xilinx 7.1i and test bench o/p show correctly(0-1-2-3-0). But when I download to XC9572 cpld it show on 7-seg display as down counter (0-3-2-1). I attached my sch file for your ref.
What's wrong with my sch or any...
chip viewer failed.
when I open assign package pins in Xilinx it is stuck on "Launching Application for process "Assign Package Pins". It take too long and I have to do "end task " and at that time "chip viewer failed" msg appear.
I am using xilinx 5.2i (XC9572CPLD), I can use assign pin after...
modelsim expecting macromodule module primitive
Why this code is appear for me even simple verilog program. Every time I have to reopen .v file and find a lot of define (that I never key in) and delete.
the following is some of warning:
ARNING: tbw.tfw(21): Bad name in macro definition...
powerline communication is very popular last 5 years. But not much popular at this time or may be I didn't notice that.
Which book is best to learn this technology and suggest me should I learn about this.
I plan to do AM simulations (block by block, means mixer, modulator, demodulators...). Which simulator is suitable fo this.
I familiar with (orcad, harmonica (ansoft)). I don't want to do block diagram simulations. I want to try in circuit simulation.