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comparator hysteresis
Hello all,
I am currently using a simple latched comparator in a CT sigma delta ADC.
My question is with regards to deterministic and random hysteresis.
When I test the comparator and provide it with a very slowly rising ramp then, very close to the threshold, the...
Hello all;
Consider a sigma delta modulator with a sinc decimation filter.
The output will be a 7 bit digital signal. Power supply is 1.5V.
What I want to do is throw away roughly 100mV from the supply rails. So I want my effective output to be in the range of 0.1 to 1.4V. Hence I want the...
Hello all;
Consider a sigma delta modulator with a sinc decimation filter.
The output will be a 7 bit digital signal. Power supply is 1.5V.
What I want to do is throw away roughly 100mV from the supply rails. So I want my effective output to be in the range of 0.1 to 1.4V. Hence I want the...
Hello all,
I have a 3V i/p signal coming from an external RC pole (500Hz). The external resistance of the RC pole is not fixed but assumed to be in the 1k region. After the "almost" dc signal is passed on chip it needs to be divided down by 2 as power supply is 1.5V. It then feeds into a sigma...
sigma-delta single ended
Consider a simple first order single ended sigma delta modulator (RC integrator).
Being single ended one terminal of the RC integrator and comparator sits at the common mode level. Being a dc signal it causes spurs in the o/p spectrum. Is there a way of resolving this...
This has puzzled me a bit today.
Scenario 1)
Consider a fractional-N PLL. The VCO frequency goes into a chain of 2/3 dividers which are set by the sigma-delta modulator. The SDM works with a 16bit input word and produces a 3 bit output. Hence the divider divides by either N-3, N-2, N-1, N, N+1...
Hello all,
this might be a trivial question but I was wondering how people go about checking whether there are no unintended connections in large designs.
Obviously, a "check and save" will reveal unconnected lines and also whether the signal lines have the same number of bits as the blocks...
Hello all,
So I was wondering how to choose the reference voltage for the DAC in the sigma delta ADC. Considering a 1.5V process the input sinusoid is centred around 750mV. With the quantizer levels of 1.5V and 0V what value do I need to feed back to the input. If I were to use 1.5 and 0V as...
I often read that " Phase noise performance is degraded by frequency multiplication at the rate of 20 log (N) whereas N being the multiplication factor".
Could someone please share their insight as to where this "20 log (N)" term comes about? Some literature references would be nice.
Thanks.
delta-sigma dead band
Hello,
I'm going for a job interview and a big part will be questions on delta-sigma A/D converters. I am wanting to prepare and would appreciate some feedback as to what might be asked.
BTW, it will be telephone interview at first.
cheers,
Ps I am familiar with the...
JITTER QUESTION
I was modeling jitter as a random variation of the clock edges. So I randomly delay or advance a jitter free clock to obtain my non-ideal clock.
Now, since I have no experience with real life clocks I was wondering about the following:
Can it happen that one edge of a clock...
divider jitter
I was wondering:
I have a system clock with total jitter J1 and then divide the clk-frequency down by a factor of M, does this mean I divide my J1 also by M?
Can someone shed some light on this?
Thanks a bunch.
Hello,
When using an IDEAL VCO in VerilogA to generate a frequency modulated signal, then the instantaneous frequency of that signal is proportional to the modulating input signal. When using VerilogA to measure the period of the FM signal and thus finding the frequency I can sample these...
Hello,
I have a question whether/what relationship there is between the probability function and the power spectral density.
For example: If we consider data converters. When quantizing a signal then we often assume that the introduced error is uniformly distributed between -q/2 and q/2. Here...
I have a question about decimation filters. As an example consider a 1st order sinc decimation filter which has one integrator operating at Fs, and a differentiator operating at the decimated rate Fs/R.
Also, assume the output of the sigma delta modulator is a 1 bit binary signal, i.e. 0, 1, 0...
I was wondering whether there are any simplification/rules when doing modulo 1 arithmetic.
For example: <a+b>*<c+d> = ? or <a+b>^2=?
Here, <> is the fractional part, i.e <4.2> = 0.2
There is plenty I could find on mod N arithmetic with n>1 but nothing on mod 1.
thanks for any tips.
Svensl
Consider a sequence (an) that is uniformly distributed modulo 1.
We know from the equidistribution theorem that:
N--> infinity 1/N Σ[ f((a•n mod 1) ) ,n=1..N] can be re-written as ∫(f(x)dx, x=0,1).
See, www.en.wikipedia.org/wiki/Equidistribution_theorem
In my case I also have a modulo 1...
Please consider a duty cycle signal (one period only for illustration).
Let's assume the period T is fixed and only the "on-time" α varies. Also assume that the height of the pulse is 1. The area under the on-pulse is given as A=1•α.
Can I represent the same signal as a signal with 50% duty...
max2620
I have a Max2620 and would like to build a hartley oscillator with it. The datasheet gives an exmple circuit for a Colpitts oscillator. See Figure 1. I was wondering whether I can use a Hartley tank with the Max2620. See Figure 2. Will this work? It could be that I distrub internal...
I would like to build a circuit for a hartley oscillator and was wondering what design to best go for. The frequency should be around 500MHz. So I was thinking about whether to use discrete components and use an ugly board construction or rather go and buy an oscillator chip to which I can...
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