Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
Hi, If I use larger channel length device (say 1um) in a 90nm CMOS process, will my maxing safe operating voltage at drain and gate, scale linearly or will it be still be 1V given by foundry for 90nm gate length CMOS? Thanks.
Thanks Klaus. I was asking in general for a wireless transmitter or a receiver. Is there any reference for power detection through vxi? Why someone will use it and Why voltage rms detection won't be sufficient for power detection? Thanks.
thanks sunny , can you explain a little better? what do you mean by linear gain?
- - - Updated - - -
thanks crutschow, so are you saying input difference is low due to negative feedback and is not dependent on open loop opamp gain? that's where I am confused. so if I make a single stage or two...
I am still not clear what is the physical mechanism that makes opamp inputs track each other? we say it is because opamp has high gain. can someone explain better. how high a gain is needed? thanks.
Thanks that helps but would it matter if it's BJT versus FET in that case there is no charging of gate capacitance is required, so we can go infinitesimally lower in current?
I just pulled it from air since you asked, if you can give some example that will be enough for me, i just want to know the procedure of doing it as I asked in the previous message. Thanks.
It's not given. I need to compare a bias voltage against fixed threshold and then clamp it to the threshold voltage. Let's say 100ps. Is there an example from scratch? Curious what is the calculation to determine the required current from response time and what device size will i choose? Thanks.
I want to make an analog control circuit like a DC comparator with BJT or CMOS, using a differential type of structure. How do I know how much current do I need to to use for biasing and what basis should I choose my device size? Can someone help or point me to any book or example how it is...
Hi nitishn5, Thanks for explaining. I am still wondering, what can go wrong from you statement "And if Node_h cannot handle it, it will be screwed". I have similar scenario. Can you please explain. Thanks for patience.
I don't know thats why I am asking in this forum. Application is low noise amplifier design, using BJT or CMOS, whats the effect of collector resistance or drain resistance on noise . No book tells me when to consider current and when to consider voltage noise of a resistor while analyizing...
Sorry GoldSmith, I am not asking the definition noise. i am asking voltage noise will increase with resistance but current noise will decrease with resistance, so in designing circuit what should one do, increase or decrease the resistance? Thx.
Hi, Can you please help me understand the noise of a resistor so that I can analyze noise behavior in a circuit? An example would be helpful.
The noise voltage is directly proportional to resistance R in a resistor but noise current is inversely proportional to R. So should one increase a...
Thanks. So does it mean its opposite. I will have 3dB more noise power that means I should measure -97dBm in the earlier example I gave? I am confused...I want to understand only in terms of noise power not noise figure..
This site uses cookies to help personalise content, tailor your experience and to keep you logged in if you register.
By continuing to use this site, you are consenting to our use of cookies.