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  1. I

    [help] rippled/gated clock warning

    Module A (input wire clk, input wire rst , ..... // other input, output reg sram_clk, ... // ohter sram control signal ); ... //use FSM to produce the sram_clk signal st0: sram_clk <= 1'b1; st1: sram_clk <= 1'b0; st2: sram_clk <= 1'b0; st3: sram_clk <= 1'b1; endmodule Module B (input wire...
  2. I

    [help] pt's error when read sdf

    pte-014 pt ##Worst case working condition read_sdf /direct/sh-home/kevin.sheng/design/809_i2c/layout/2006_0104_from_layout/pmp_dig_slow.sdf -type sdf_max Warning: The SDF file is version 3.0. Current SDF-3.0 supported constructs are: REMOVAL, RECREM, RETAIN and CONDELSE. (SDF-026) Error: No...
  3. I

    [help] how to set_dont_use in soc encounter?

    set_dont_use when insert buffer to fix timing. I want to use buf4, not buf16 and so on... But how to tell the soc encounter dont use those cells ? thanks
  4. I

    [help] how to set toggle value?

    there is a option about "toggle value",which is between 0-1 ,when analyze the power consume in soc encounter. How can we know which value should be set? What factors should be consideration? Thanks in advance. :)
  5. I

    [question] tcl script in design compiler

    design compiler tcl current_design top set ALL_DESIGN [get_designs *] foreach_in_collection a $ALL_DESIGN { current_design $a set_fix_multiple_port_nets -buffer_constants -all echo "** set_fix_multiple_port_nets at design $a ***" } and the result is :Current design is 'mux21_15'. **...
  6. I

    how to insert buffer for high fanout net

    set_auto_disable_drc_nets such as clock ,rst port.. I just want insert the buffer in synthesis , not leave it for the apr tools . I had done the following things: set_auto_disable_drc_nets -none in each submodule of the design. set_max_fanout 15 for clock and rst signal...
  7. I

    [question] a warning fanout

    Warning: Design 'top' contains 2 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) Is there any command to list which nets have high fanout? thanks
  8. I

    Statement unreachable (Branch condition impossible to meet)

    branch condition impossible to meet) When I read_verilog , this warning come out. And a strange things happend when I check my code: there is a case sentence in the code: case(current_state): `IDLE: ..... ...... `READ: begin wr<= ~wr; //here is the probem ...
  9. I

    how to use insert_pads?

    insert_pads Dear members, I using the following script to insert_pads, .......... compile set target_library io.db set link_library io.db current_design top set_port_is_pad [get_ports *] insert_pads and the...
  10. I

    how to use set_fix_multiple_port_nets?

    set_fix_multiple_port_nets first I read in the design and link,then I set the current_design top(top is the top level design). ..... curret_design top foreach_in_collection design [ get_designs "*" ] { current_design $design set_fix_multiple_port_nets -all -buffer_constants } compile wrtie -f...
  11. I

    a warning about design compile: fanout

    Warning: Design 'top' contains 2 high-fanout nets. A fanout number of 1000 will be used for delay calculations involving these nets. (TIM-134) How to eliminate this warning? use command set_max_fanout? thanks in advance
  12. I

    [question] a warning about design compiler

    warnings design compiler a top design ,and a ,b,c sub design. a ,b had been compiled and set_dont_touch. and now read in a, b,c and top,when link, the following waring come out: Design 'a.db:mux21_3' comes before design 'b.db:mux21_3' in the link_library; b:mux21_3' will be ignored. The...
  13. I

    [help]:how to know which cell was used in a design

    How to know which cell was invoked and the times invoked in a design? Does Design Compiler have the corresponding command? I had search the report_* command, but can't find such command.:( thanks in advance
  14. I

    [help]:how to know which cell was used in a design

    How to know which cell was invoked and the times invoked in a design? Does Design Compiler have the corresponding command? thanks in advance
  15. I

    [question]: about synopsys dc constraint

    If a module ( clk, b,c),clk is clock ,and b is input port. Is the following command useful ? set_min_delay 0.00 -from [get_clocks {CLK}] -through [get_ports {b}] I think there is no path between the clk and port b .. thanks in advance
  16. I

    [question]: synopsys dc constraint to cadence gfc

    I use the pearl cmd: read_dc_script -log aa.log -hpin_log aa_hp.log -retain DAC.dc top_con.cmd write_gcf top_con.gcf to convert the dc constraint script to cadence's constraint. But it seems the pearl can't recognize the set_input_delay and set_output_delay command. so I must modify the gcf...
  17. I

    Any tool to get timing library

    hi members, After layout ,we can get many materials,such as sdf,gdsII .. And I want to know,if there is any tool can extract the timing information and produce the timing library which can be used by synopsys design compiler? just like the following format: library(USERLIB) {...
  18. I

    read_verilog in dc_shell-t

    read_verilog netlist I use this cmd: read_verilog -netlist filename.v, and the following error come out: Error: /export/home/cad90/050201-01/filename.v:2820: Unknown Construct in expression (VER-700) Error: /export/home/cad90/050201-01/filename.v:2820: Unknown Construct in expression...
  19. I

    Question about sdf file in DC

    a question about sdf when I read the sdf file in dc following the steps: read_verilog current_design create_clock set_propagated_clock set_input_delay set_output_delay report_timing .. but the dc told: Information: Annotated 'cell' delays are assumed to include load delay. (UID-282 )...
  20. I

    replace in mentor epd(eproduct)

    mentor epd Does the mentore eproduct support regular expression when replace? For example: I want to replace label D[0:n] with Data[0:n], how should I do in EPD? Thanks in advance

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