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it will infer flops only but that is bad coding style.
use non blocking statements and u can change order of those assignments
if u want to use blocking then u have to aware of sequence of the assignments to be write
u can implement in two ways
1. in first stage 2 inputs are given as input the left out input will be added to 2nd stage like that u can draw until u reach to the end with single output.
2. apply first two inputs to first xor gate out put of this gate is combined with new input for next...
it specifies according to the application
When u r dealing with different speed devices, that signal will be asserted from first line to last line depends on device
for faster devices, the signal will change quickly
for slow devices, the signal will change late
so it is like range to get...
inverter using mux
hi vlsi technolgy
i hope i designed not gate correctly.
as he didn't mentioned abt nor gate i didn't draw
and ur's design for nor gate is correct yaar
and thanks for helping out
Re: vhdl packages
If the operands of STD_LOGIC type, one has to use .arith package which is provided by IEEE to perform any arithmetic operations ( In the package they defined resolve when the operands taking other than '0' and '1')
Eg if X = z; Y = x; then if RESULT = X * Y; then what will u...
For finding 2's compliment first search for '1' from LSB and put upto that position as it is and the remaining bits ( upto MSB ) compliment the bit.
for searching '1' frm LSB we can use priority Encoder by prioritizing LSB as highest priority
Re: Mux question
with four bit the possible prime no are 2,3,5,7,11,13
y = f(A,B,C,D) = ∑(2,3,5,7,11,13);
...........D __| |
.....C & D __| |------ Y
notC & D __| |