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  1. B

    combo logic /latch inference

    hi it will infer flops only but that is bad coding style. use non blocking statements and u can change order of those assignments if u want to use blocking then u have to aware of sequence of the assignments to be write
  2. B

    19 input XOR gate with 2 input XOR

    hi u can implement in two ways 1. in first stage 2 inputs are given as input the left out input will be added to 2nd stage like that u can draw until u reach to the end with single output. 2. apply first two inputs to first xor gate out put of this gate is combined with new input for next...
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    question on a shadow waveform?

    it specifies according to the application When u r dealing with different speed devices, that signal will be asserted from first line to last line depends on device for faster devices, the signal will change quickly for slow devices, the signal will change late so it is like range to get...
  4. B

    What is the maximum frequency of this circuit?

    what is the maximum frequency of the circuit given below:
  5. B

    AND,NOT,OR,XOR,XNOR,NAND,INVERTER using MUX

    inverter using mux hi vlsi technolgy i hope i designed not gate correctly. hi venkat_kvr as he didn't mentioned abt nor gate i didn't draw and ur's design for nor gate is correct yaar and thanks for helping out
  6. B

    AND,NOT,OR,XOR,XNOR,NAND,INVERTER using MUX

    nand using mux Realization of GATE USING MUX If any one finds wrong in this reply me If u other design share with us with regards khalandar basha basha_vlsi@yahoo.co.in[/img]
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    What exactly is the Verification IP?

    Re: Verification IP To provide testing block inside the design along with the DUT which is called built-in-self test while power on the system this checks the entire system
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    Software used for simulation of basic VHDL

    Re: about VHDL... many vendors provide simulators for simulating HDL designs modelsim by mentor graphics ISE by Xilinx ncsim by CADENCE i am not aware of free simulators which works for all designs
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    The diffences between unsigned.all, numeric.all and arith.all (VHDL)

    Re: vhdl packages If the operands of STD_LOGIC type, one has to use .arith package which is provided by IEEE to perform any arithmetic operations ( In the package they defined resolve when the operands taking other than '0' and '1') Eg if X = z; Y = x; then if RESULT = X * Y; then what will u...
  10. B

    How long will it take to shift an 8-bit number into 8-bit serial in, parallel out?

    Re: register question For SIPO it takes 8 Clk pulses For SISO it takes 15 Clk pulses For PISO it takes 8 Clk pulses For PIPO it takes 1 Clk pulses
  11. B

    TWO"S complement

    For finding 2's compliment first search for '1' from LSB and put upto that position as it is and the remaining bits ( upto MSB ) compliment the bit. for searching '1' frm LSB we can use priority Encoder by prioritizing LSB as highest priority
  12. B

    Blocking and Non-Blocking assignment

    blocking and non-blocking in vhdl Both statement blocks are correct. But using non blocing stmt assignment is good practice and using blocking stmt is bad coding style
  13. B

    validation of a project means what ?

    Validation is checking the design after it exists physically ( checking functionality of IC) . verification is done after coding
  14. B

    Regarding reusing a checker in the system level

    Re: regarding checker Which HVL you are using for verifying
  15. B

    System using a 4:1 MUX that identifies whether a 4-bit number is prime

    Re: Mux question with four bit the possible prime no are 2,3,5,7,11,13 y = f(A,B,C,D) = ∑(2,3,5,7,11,13); ...........C __|\ ..................| \ ...........D __| | .....C & D __| |------ Y notC & D __| | ...................| / ...................|/...
  16. B

    regarding Bluetooth Baseband Controller

    wat r the issues ur having metion clearly
  17. B

    Cadence Virtuoso Question

    those options r used to analyze ur design. ie to do dc , ac transient analysis

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