Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. D

    The green wire for color signal transmission in color TV

    Hi all, I have a querry on the color signal transmission in color TV. While transmission, the color difference signal is used using the red and the blue component.The green component is not used. My question is - why the green component is not used? Thanks and regards, dak-ju
  2. D

    What does FDMA stand for?

    Hi, I want to know what is fdma? In what way Is it different from dma(dynamic mem. access)? Regards dak-ju
  3. D

    Explain me concept of virtual clock in constraining design

    virtual clock Hi can anyone explain me the concept of virtual clock in constraining a design? Regards dak-ju
  4. D

    false path in constraints

    Hi everyone, I want to know what are false path and why are they being set in constraining a design? Thanks in advance, dak-ju
  5. D

    Problem with synthesis of VHDL code

    synthesis problem Pls have a look at the following code in vhdl if(clk'event and clk = 1) then x <= y; z <= x; end if; When I synthesize the code the rtl simulation shows z to be one clk cycle delayed version of y while in the netlist simulation it shows z to be two clk cycle...
  6. D

    Why read and write pointers are gray encoded in FIFO design?

    asychronous fio design I want to know why in the asynchronous fifo design , the read and the write pointer is gray encoded?
  7. D

    Logic design for detecting clock edge

    I want to detect the whether the rising edge of signal 2 is synchronised with the rising or falling edge of signal 1.(Plese refer the attached picture) So I need a logic design to implement it. S1 and S2 are input to my system Actually I need to shift the signal s2 by one complete period of...

Part and Inventory Search