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    Audio Feature Extraction in VHDL

    What i am asking is just a small push or something.... We have decided on the algorithm...which will use Hidden Markov Model (HMM) but this is the comparison part. I want to learn what steps should be followed in order to make the incoming voice signal through microphone comparable.... There...
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    Audio Feature Extraction in VHDL

    audio vhdl Hello folks, I am a beginner to VHDL. I have basic knowledge of VHDL programming. I have to use VHDL for my final project now where i have to implement speech recognition using FPGA. Starting first can anyone guide on how can i extract various features of a speech signal using...
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    Speech Recognition VHDL

    speech recognition vhdl Thanx for the reply....it gave me a good starting point.... I have seen everyone talking about filters. For out initial design we will use the - DSP micro controller to process the incoming analog siganl. It will filter and sample the signal to digital. - Then the...
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    Speech Recognition VHDL

    vhdl speech recognition Hey Guys, VHDL HELP I am a beginner to VHDL. I know how to write basic codes in VHDL. I want to implement a Speech Recognition system using FPGA. So i want to learn how to design the code in VHDL. For that i have to learn the very basic of Signal Processing or Analyzing...
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    Problem with signal state_reg in simple traffic light controller

    Re: Simple traffic light Hey thanx for the Solution...now it works...cool!!
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    Problem with signal state_reg in simple traffic light controller

    hey guys i hope u can help me out... i want to design a simple traffic light controller according to the 4 states shown in the code below. my only problem is that my signal state_reg is not changing form one state to another. this is because the counter i included in the the code as a process is...

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