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  1. isaacnewton

    result of THD calculation in Cadence

    calc.pdf cadence I was trying to using Cadence Calculator to calculate the Total Harmonic Distortion (THD). I got the result something like "0.012m". Can somebody tell me whether it is in Percentage or not? In other words, the THD is 1.2% or 0.0012%:?: Thank you in advance:!:
  2. isaacnewton

    ADS Design Kit - TSMC018um CMOS

    tsmc018um In this ADS Design Kit, there is a file: mm018_dk.net. In this file There are 12 different models for the same device: model TSMC_CM018RF_BB_MODEL_nch BinModel Model[1] ="TSMC_CM018RF_BB_MODEL_nchx1" Model[2]="TSMC_CM018RF_BB_MODEL_nchx2" Model[3]="TSMC_CM018RF_BB_MODEL_nchx3"...
  3. isaacnewton

    How to do Input Referred Noise simulation?

    Input Referred Noise is one important parameter for an operational amplifier. Can any one tell me how to do this kind simulation? Thanks.
  4. isaacnewton

    LVS:4 netlist ambiguities were resolved by random selection

    After I done the LVS, I was told 4 net-list ambiguities were resolved by random selection. And I was also told: The net-list match. Can somebody tell me what's going on there? How can I fix it? Do I have to fixed before send it out? If I send the layout to fabrication, will the circuit work...
  5. isaacnewton

    Short-channel MOSFETs

    vds(sat) On page 297 of Baker's book CMOS: Circuit Design, Layout, and Simulation 2nd Edition www.cmosedu.com/cmos1/book.htm Equation 9.54 Vov = VGS - VTH ≠ VDS,sat How to understand this? How do define VDS,sat for short-channel MOSFETs? The short channel effects is only for very...
  6. isaacnewton

    Bipolar Transistor in CMOS

    gds transistor Can somebody tell me what are the structures of PNP and NPN transistors in TSMC 0.18um CMOS technology? Thanks in advance. www.mosis.org/products/fab/vendors/tsmc/tsmc018/
  7. isaacnewton

    How to understand this Bias Circuit?

    There are 3 branches in the this circuit. In order to get Equation (14) and (15). The currents through those 3 branches should be equal. I don't understand why the currents through the 3 branches are equal.
  8. isaacnewton

    Metal Width for VDD/VSS

    If the total current is 1 mA, what's the Metal Width (layout) for VDD or VSS? Thanks.
  9. isaacnewton

    L for TSMC 0.18 um in Analog or RF design

    If TSMC 0.18um CMOS is used to design analog circuit (like op amp), what the change length L do you suggest? :?: How about 1 um?:?: Thank you in advance.
  10. isaacnewton

    How to analysis this circuit?

    How to analysis this circuit? What's the advantage and disvantage of the circuit? Especially, the circled part. The circuit is copied from Razavi's book. Page 132, Figure 4.39.
  11. isaacnewton

    Maximum Oscillation Frequency fmax

    maximum oscillation frequency The definition of Cutoff Frequency fT is the frequency at 0dB current gain. What's the definition of Maximum Oscillation Frequency fmax? I tried to use google searching, could not find it. Thanks
  12. isaacnewton

    A Question about an Op Amp

    The attached picture is the simplified equivalent of TLC274 op amp. http://www.hep.upenn.edu/SNO/daq/parts/tlc274.pdf Can somebody explain why they put R1 and R2 at the input (the Gates of P1 and P2)? Thx.
  13. isaacnewton

    A question about an Op Amp

    The attached is the circuit schematic of an op amp. Can somebody explain the Functions of Q7, Q11 and R1? Why do we need them? Thank you in advance.
  14. isaacnewton

    [SOLVED] Quiescent Output Voltage

    The attached is a schematic of a simple op amp. I have question about the Quiescent Output Voltage of this op amp (open loop) or the Base voltage of Q6. How to calculate it by hand. It looks like the quiescent output voltage of this op amp is not well controlled. Thank you in advance.
  15. isaacnewton

    Why there are TWO capacitors?

    The attached figure is a application circuit of Op Amp. Can somebody tell me why there are TWO capacitors (0.1 uF and 1 uF) tied to the voltage supply Vs? Why not just use ONE capacitor with value of 1.1 uF? Thank you...
  16. isaacnewton

    ACTIVE and SELECT layer

    Can someboday explane the difference of NACTIVE, NSELECT PACTIVE, PSELECT in fabrication layout. Thank you.
  17. isaacnewton

    Cut off Frequency fT for TSMC 0.25 um CMOS Technology

    tsmc 0.25um cmos technology Hi, Who knows the cut off frequency fT for TSMC 0.25 um CMOS Technology? Thank you. www.mosis.org/Technical/Testdata/tsmc-025-prm.html
  18. isaacnewton

    Is the lambda here a channel-length modulation parameter?

    LAMBDA ? Hi, I have a question about Channel-length modulation parameter - lambda. I copied the following from: www.mosis.org/cgi-bin/cgiwrap/umosis/swp/params/tsmc-025/t4cs_mm_non_epi-params.txt Is the 'lambda' there channel-length modulation parameter? Thank you. Copied from mosis.com...
  19. isaacnewton

    Propagation Delay of Schematic VS Post-layout Simulation

    propagation delay between schematic layout Dear All, I am designing a 4-bit ALU (Full Custom Design) using Cadence. I did schematic simulation and post-layout simulation. I found the propagation delay for the schematic simulation is even greater than that for post-layout simulation. The delay...
  20. isaacnewton

    How to remove spikes in Digital VLSI design?

    how to remove spikes Hello Everyone, This question is about Digital VLSI design. The attached Figure is the post-layout simulation of 4-bit ALU. From the figure, you can see there are lots of SPIKES (circled parts). Does anybody has seggestions about how to remove or alleviate those spikes...

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