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    Assignment MUXs in Verilog

    One thing in Verilog always gives me fits: assign data_out = ((output_select == 3'h01) * {2'b0, saved_rx_data[12:7]}) + ((output_select == 3'h02) * {1'b0, saved_rx_data[6:0]}) + ((output_select == 3'h03) * 8'h00); This statement only produces 1 bit because of the logical equal-to sign...
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    Quartis II and Verilog: Stealthily skipping code synthesis?

    Here's a little feature with Quartus II that's giving me fits. I'm trying to create a PLD project using Verilog in Quartus, but I have a bug in my code somewhere. Because of the bug, though, Quartus is deciding to optimize my design. A large portion of my design is no longer being synthesized...
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    Do you use auto-route for PCB layout packages?

    How many of you use the auto-routing functions in your PCB layout packages? I'm torn between using it or doing everything by hand. I typically work with *very* low volume boards (3-4 max). On on hand, I save a day of labor by going the auto-route route. On the other hand, manual labor looks...
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    Total Static Error on an ADC

    How exactly do you come up with the total static error for an ADC? I know you have factors like the gain, offset, INL, and DNL that factor into the static ADC error. But... how would you go about putting them together and obtaining an overall error number? I want to be able to say, "this ADC...
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    Icarus Verilog doesn't support generate?

    icarus verilog generate I'm trying to work through some of the examples found in Samir Palnitkar's "Verilog® HDL: A Guide to Digital Design and Synthesis, Second Edition". I'm using Icarus Verilog since it's free. The problem I'm running into is that Icarus doesn't seem to support generate...

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