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  1. E

    How to improve PSRR of a BGR?

    BGR PSRR simulations You sim is correct. The only way to improve PSRR- is to use a differential output BGR.
  2. E

    wide range LO generation question

    If you can increse your VCO range to cover an octave then a programable divider can be used to generate any lower frequency you wish. If your VCO canot be adjusted to cover an octave then you can augment it with an auxilary circuit to generate a Fvco*0.75 output. This is done by taking the VCO...
  3. E

    Fractional Synthesizer question

    Yes the FRacN PLL is a good option. The PLL bandwidth should be set to smaller than 50kHz if at all possible to reduce spurs at the output. ADI has a free downloadable program to simulate operation with thier PLL. See: http://forms.analog.com/form_pages/rfcomms/adisimpll.asp
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    FracN PLL phase noise problems and questions

    Re: FracN PLL phase noise A increse in low frequency noise when the fractional part is ≠is very common and due to the fractional noise "folding" into the lower frequency range due to nonlinearities in the diveder/phase-detector/chargepump. One way to reduce the effect is to add a very small...
  5. E

    LC-VCO simulation using HSpice

    The transient step size must be set really small. Otherwise it indroduces a loss which cam case a high-Q circuit to not oscillate in spice. You may need to do some trial & error. As a srarting point use a step size of 1/1000 of the period.
  6. E

    Why is the noise floor calculated from kT?

    4ktr noise The available noise power from any resistor is kt = -174dBm/Hz. The open-circuit noise voltage density for a resistor is: sqrt(4ktR). To deliver the available power to a load the load needs to be a conjagate match. So given a source of value R and a noise-less load of value R the...
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    how to simulate the influence of VTH difference on the

    Add a voltage source in series with the gate of one of the two transistors. Set the voltage to the Vth difference you want to simulate.
  8. E

    How much will two NMOSFET with the same dimension differ?

    Re: question on mismatch To get the best result: 1: Use large area devices. For example dont use a 1um x 0.18um instead use a 10um x 1.8um. The larger the area the better they will match. 2: Make sure to scale W & L so the are deeply in saturation. This typically means that W should not be too...
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    Help me design a 80dB opamp with 10uF capacitance load

    Re: A OPAMP design The classic solution is to put a resistor in series with your load capacitor. Then at high frequencies the opamp load looks like a resistor. For example iof you place a 1kohm in series with your 10uf load the result at high frequencies will look like you are driving a 1kohm...
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    Which via is good, with big dia or with small dia ?

    Re: question on VIA Generally you want low inductance so a large surface area is desierable. Multiple small vias typically will work better than 1 large via since the total surface area will be greater.
  11. E

    Whats the minimum NF for a CMOS LNA for 2.4GHz?

    Re: NF for LNA For WLAN where you do not have big blockers the lna can have a lot of gain so the noise figure can be low. At 0.18um cmos a NF of 1.5dB is fesable. The input network Q will be high which can effect linearity as well as component variation sensitivity.
  12. E

    can i set the current mirror ratio to 20:1

    With CMOS you should be ok scaling down currents. Scaling up can be an issue because any input noisae will alsi scale up.

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