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    How to deal with gated clock in Synopsys Formality?

    I used DC to compile the design and dumped the svf file too, after Formality reading the svf file, it wrote a file(svf.txt) that contants the statement "guide_environment \ { { clock_gating latch_and } }", so I don't get the reason why Formality still doesn't pass the verification.
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    How to deal with gated clock in Synopsys Formality?

    Hello, I compiled some gated clocks in my design, and when I do formal verification, the gated clock cells are in unmatch cell list, how can I tell Formality about the gated clock setting? Regards,
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    How to get off some cells like "**SEQGEN**" in DC

    Hello, I want to compile my design to gate-level with DC, but I always got some cells like **SEQGEN** in the netlist, I have no idea about the reason, that seems like I didn't finish the compiling, is the anyone knows that? Regrads,
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    How to stop simulation in VHDL testbench?

    Hello Devas, Yes, the statement works! Thanks a lot! Regards,
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    How to stop simulation in VHDL testbench?

    Hello, I don't know how to stop my simulation, my testbench is described in VHDL and I use ncsim, is there any method to stop the simulation just like using $stop, $finish in Verilog? Regards,
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    clock multiplexer problem - help needed

    clock multiplexer Ok, thanks, I'll try that.
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    clock multiplexer problem - help needed

    Re: clock multiplexer If I do so, how do I to do the timing analysis with PT, should I set case analysis since I have a multiplexer on the clock path?
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    clock multiplexer problem - help needed

    clock multiplexer Hello, I have two input clocks, CLKA and CLKB. They go to a multiplexer directly from input port then generate a new clock CLK_SYS as the system clock of the whole circuit, but the select signal of the clock multiplexer comes from the CLK_SYS domain and its value is not a...
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    Constraint on Multi-Clock with a same source

    Since the definition of the two clocks are separately, and the frequency are different too, so how to tell DC that the two clocks have a same source?
  10. B

    Constraint on Multi-Clock with a same source

    Yes if I have the whole circuit, the key is that CLKA and CLKB are all input clock, so I can't do that ..
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    Constraint on Multi-Clock with a same source

    Hello guys, In my design, we have multiple clocks with different frequency, but the clocks have the same source. (For example, clock A and clock B both are divided from clock S, and Frequency(A) = n*Frequency(B), n is an integer) There are some logic between the two clock domains, how can I...
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    Constraint on combination logic in DC

    set_max_delay Well, I think your suggestion is right, setting constraint like that will not get any vioalation. Thanks!
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    Constraint on combination logic in DC

    set_output_delay in dc Hi all, I use Synopsys DC to compile my design, and in the design: A is the input, B is a sequential logic output of it, and C is a combinational logic output of it. In my constraint file, for sequential part, I set constraint like below: create_clock -period 20 -waveform...
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    DC_SHELL constraint about input delay and output delay

    input delay Ok, thank you so much! Best regards,
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    DC_SHELL constraint about input delay and output delay

    input delay and output delay Hi Guys, I am confused with the command "set_input_delay" and "set_output_delay": The clock frequency is 50MHz. For constraint on a path from input pin to a DFF, I want the logic between input pin and the DFF to take only 5 ns, should I use "set_input_delay -max...
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    Formality failed to read .svf file with syntax error report.

    .svf file Hi, The issue has been solved, the reason is the old version number of Formality indeed, I updata Formality to the latest version and the .svf file works. Thank all of you!
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    Formality failed to read .svf file with syntax error report.

    svf read Hi Guys, I meet an issue when I read .svf file with "set_svf ./svf_name.svf", that generated an error report: ################################## line 1: syntax error at 'c' Error: Invalid SVF, contents ignored (FM-339) 0 ################################## I generated my svf file...
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    How to convert a number string to several integer?

    Hello, I want to convert a number string to several integer with VHDL language, for example: convert 1112131415 to 5 integer -- 11,12,13,14,15. Would anybody like to help me to solve that? Thanks!
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    A question about VHDL TEXTIO

    vhdl textio read Dear aji_vlsi, You are right, I have modifid my stimulus file(the bottom line of the file is empty), and the simulation is successful now. Thank you!
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    A question about VHDL TEXTIO

    vhdl textio Hello, I'm trying to read some stimulus form a file, but an error always occur, would you like to help me to solve it, thanks. Source code: library ieee; use ieee.std_logic_1164.all; use std.textio.all; entity FILE_READ is generic ( stim_file: string...

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