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  1. S

    HD3 and THD measurement in cmos ota using cadence

    cmos ota design in cadence how to do PSS analysis??
  2. S

    DC analysis of mos differential amplifier

    cmos differential amplifier hii thanx for your reply i want to plot gm Vs Vin and differential output voltage Vs diff input voltage. I hav used a simple pmos current source load and diff pair are of nmos...so it converts diff input signal to single ended output signal. I am not able to make...
  3. S

    DC analysis of mos differential amplifier

    mos differential amplifier hi I want to do DC analysis for mos differential amplifier in differential mode and in common mode . Please tell how to give input signals for both cases in cadence virtouso. thanx Added after 5 hours 49 minutes: anyone please reply and help me out
  4. S

    HD3 and THD measurement in cmos ota using cadence

    thd in ota anyone please reply and help me out
  5. S

    HD3 and THD measurement in cmos ota using cadence

    thd + ota please reply anyone
  6. S

    HD3 and THD measurement in cmos ota using cadence

    thd +ota hello !! how can i measure HD3 ,THD, IIP3, IIM3 using cadence analog environment for cmos ota design please reply soon......its urgent thanks in advance :)
  7. S

    what r the value of these parameters in gpdk180n

    What is the value of vthn, vthp, λn, λp, µnCox, µpCox in gpdk 180n library for simulation in cadence spectre.I am using 1.8 voltage supply. Plz reply if anyone knows. Its needed to start my ota design. thanq in advance. Added after 1 hours 40 minutes: please reply someone. Added after 2...
  8. S

    (vout1-vout2) Vs (vin1-vin2) plot using cadence

    please reply..........its urgent. Added after 2 hours 28 minutes: if anyone know abt this problem then plz reply how to do that..
  9. S

    A question that is about the bias of a NMOS transistor

    on comparing mosfet lenghthwise, it acts as a voltage divider. so as the length increases voltage also increases. Thats why vds increases with L.
  10. S

    (vout1-vout2) Vs (vin1-vin2) plot using cadence

    how can i plot the curves shown in pic using cadence virtouso spectre. i need plot of diffrerential input in my design. plz guide!!! thanx in advance...
  11. S

    Digital design question..

    simply xoring will give the previous input............isntit the ckt will be xor gate........
  12. S

    finger width in mos properties

    i dont know whthr it is concernd wid m factor............thr is 1 option in mos properties as finger width ...........i m not getting watz that......
  13. S

    finger width in mos properties

    Reply with quote Edit/Delete this post Delete this post Report this post to the moderators of this forum while working in cadence virtouso.....i came across a property of mos(n or p) thr is a option finger width.........watz this ?? n also in layout in property of mos thr is option threshold...
  14. S

    wat do u mean by combo logic??

    hey can u tell frm whr i can get some more clear idea
  15. S

    Looking for Virtuoso tutorial on analog analysis

    Re: virtouso manual it is .rar extension........right?? i m working on linux(red hat) plateform in wich the file is not able to open...
  16. S

    Looking for Virtuoso tutorial on analog analysis

    Re: virtouso manual thnx .....4 ur favourbt the file is not opening......... can u chek it once n then post it again.
  17. S

    Looking for Virtuoso tutorial on analog analysis

    hey does ne1 hav cadence virtouso help manual regarding how to do various digi n analog analysis lyk delay, power,pdp,min n max vdd,noise ,rms value,capacitance,....................n al that. plzzzz its urgent!!
  18. S

    floating point adder using virtouso

    hey can ne 1 help me in getting a spice realizable architecture of floating point adder?? i started wid designing d same but not able to make shifting of exponents........... plz guide me.......
  19. S

    wat do u mean by combo logic??

    does combo logic means combinational logic??
  20. S

    combo logic /latch inference

    hey it will infer ffs.........since code is sensitive to clk......use nonblocking staements to avoid this case........

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