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site:edaboard.com rf ic layout
I dont know which book is completely on RFIC layout.
The guideline is normal put your sensative RF connections on top metal layer. Always be aware of parasitics. And post-layout simulation is usually necessary
settling time of VCO
For example, if you using direct phase modulation on VCO, then this settling time will effect the modulation spectrum. Thus this settling time is equivalent to modulation bandwidth this VCO can handle. So How to accurately model this settling time in simulation, how to...
It really depends on the technology, you are using a 0.6um, which should normally fits well with your simulation if it is a low frequency application.
Added after 36 seconds:
for deepsubmicron CMOS, the square law will not always hold