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  1. R

    CMOS RFIC layout considerations

    site:edaboard.com rf ic layout I dont know which book is completely on RFIC layout. The guideline is normal put your sensative RF connections on top metal layer. Always be aware of parasitics. And post-layout simulation is usually necessary
  2. R

    Resistor degrading phase noise of VCO..

    the resistors contributes noise which are converted to phase noise by am-fm conversion
  3. R

    Which book is the best for a PLL designer?

    Re: best pll book my design is rf and mixed signal, before I was doing designs like vco and prescalers. is there any other book better than what I mentioned?
  4. R

    Which book is the best for a PLL designer?

    which book is the best for a designer? best or gardner?
  5. R

    VLSI Circuit Design Video Lecture

    there are also some very interesting webcasted courses in Berkeley University available
  6. R

    Power-on circuit for LDO.

    make it switchable
  7. R

    Beginner in analog circuit design

    best book on analog circuit design PE Allen
  8. R

    What is the physical meaning of loop bandwidth of PLL?

    pll loop bandwidth good explaination
  9. R

    How to calculate the settling time of VCO?

    settling time of VCO For example, if you using direct phase modulation on VCO, then this settling time will effect the modulation spectrum. Thus this settling time is equivalent to modulation bandwidth this VCO can handle. So How to accurately model this settling time in simulation, how to...
  10. R

    temperature drift of VCO

    thanks khouly, but I think the inductor makes more contribution on temp drift, isn't it?
  11. R

    offset in bandgap design

    thanks guys
  12. R

    We are all from China

    From China Is there a university in UK good at IC design? Don't think so. Then how can UK IC companies get qualified engineers? They can't. That is why english is so weak in IC in Europe.
  13. R

    difference between the calculation by hand and simulation

    It really depends on the technology, you are using a 0.6um, which should normally fits well with your simulation if it is a low frequency application. Added after 36 seconds: for deepsubmicron CMOS, the square law will not always hold
  14. R

    What is the metal resistance found in the design kits?

    metal resistance just interconnection layer
  15. R

    How to calculate the settling time of VCO?

    settling time of VCO Well, that is a way of simulation. What I meant is, is there a rigor analysis existing on this topic?
  16. R

    What exactly is Jitter?

    what is Jitter phase noise in time domain more prescisely, you can find formulars to convert phase noise to jitter
  17. R

    How to calculate the settling time of VCO?

    How to calculate the settling time of VCO? is there formula avalible?
  18. R

    Inductor with active enhanced Q in LNA

    Using inductor with active enhanced Q as load in LNA under consideration, will this cause noise degradation of the LNA due to the cross coupled CMOS pair
  19. R

    offset in bandgap design

    site:www.edaboard.com offset bandgap How to deal with the Op_Amp offset regarding band-gap design in CMOS

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