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  1. M

    Parallel Port Data Acquisition

    Hello I want to make a data acquisition system using a micro-controller/FPGA, interfacing it with PC via parallel port. I was just wondering if I could get a sampling rate of about 1.5 Mega samples/bytes per second (assuming one sample is 8 bit long). I mean I am only concerned about the...
  2. M

    MATLAB-scanning for input and in parallel executing other part of the code

    I have a set of instructions that I want to be executed for ever, while in parallel to this execution, I want MATLAB to scan for user input that I can use to pause/resume the execution of the set of instructions. Is it possible in MATLAB. Any Suggestions please. Thanks, Best regards, Muhammad...
  3. M

    Where can I buy a transparent magnet??

    Hi! I am looking for a Transparent Magnet for my experiments. I have googled it but could not found any commercial product. Is there something available. Thanks, Best regards, Muhammad Awais.
  4. M

    2D Matrix Convolution in MATLAB.

    Hello I am trying to do 2D convolution in MATLAB. its easier to do it with conv2 function. I was wondering if I could do it like this. computing convolution in x-direction and then in y-direction using linear convolion function conv in MATLAB, and finally combining them to obtain a same result...
  5. M

    Which is better for hardware simulation, Verilog or VHDL?

    Re: Verilog or VHDL Hi! I want to add up something. If I am not wrong you also asked as what software or development tools you need? If you are working with Xilinx FPGAs then you will have to download the development and simulation tool from xilinx. that is Xilinx ISE 11 and thats free the...
  6. M

    Happy Eid UL Adha - holiday greetings

    Yes! Same to you. :) Many happy eid greetings to all muslim forum memnbers :)
  7. M

    Virtex2 pro dual port block ram

    Hi I am currently working with virtex 2 pro fpga and want to use the dual port ram, the problem I am having is that in simulation it shows right results while when I synthesize my program it does not work accordingly. I have varified this that the problem is only due to the use of dual port ram...
  8. M

    Programmable frequency divider from 1 to 32 division factor

    Re: Programmable frequency divider from 1 to 32 division fac Hi andrew! I dont know how far you are with your current design, but I had some helping material that I thaught to share with you so that you have more ideas to do with. The attached file shows how you can make a exactly an odd...
  9. M

    VHDL code synthesizeable or not, please help me

    vhdl not code Hi! I am new to VHDL, I want to know that is the following piece of code synthesizeable or not process (x) begin if(x' event and x = '0') then ..... .... end if; end process; Where x is any signal or input other than the clock. I am perticularly refering to the event statement...
  10. M

    a piece of code - synthesizeable or not?

    Synthesizeable or not? Hi! I am new to VHDL, I want to know that is the following piece of code synthesizeable or not process (x) begin if(x' event and x = '0') then ..... .... end if; end process; Where x is any signal or input other than the clock. I am perticularly refering to the event...
  11. M

    bilinear/bicubic interpolation

    bicubic interpolation Hi! I am currently working with image down sampling. Can anyone explain the basic concept and idea of image down sampling using bilinear and bicubic interpolation. Thanks, regards, Muhammad Awais
  12. M

    Frequecny division by any integer factor

    Hi thanks for the reply. Thats really helping. Thanks again. regards, Awais
  13. M

    FFT exact meaning - need correction or clarification

    FFT Simple question Hi! I want to know that what does the term "fft bins" exactly mean?. I have searched for it but could not understand it exactly. That if for a discrete signal x(n) we take an N point fft, then FFT spectrum will have N frequency bins. Is it right or wrong. Please correct me...
  14. M

    Frequecny division by any integer factor

    Hi! I want to know if there is some way to divide the input clock frequency by any integral factor e.g. a division of input clock by 3. I know its possible to divide the input clock freq. by powers of 2. But how about any other integer. thanks. regards Muhammad Awais
  15. M

    transfer data from process1 to process2

    HI! There seems no reason of data loss. Well if you can put a pieace of code that can help to understand the problem. One more thing try taking data on the next rising edge of the clock in process2, i mean instead of initiating process2 on falling edge make it a rising edge as well. then check...
  16. M

    transfer data from process1 to process2

    Hi! You can use signals to carry data from one process to other. This is the simplest solution i guess. entity architecture signal a: std_logic; begin process(clk) begin if(clk' event and clk='1') then a<=x; end if; end process; process(clk) begin if(clk' event and clk='0') then y<=a; end if...
  17. M

    Modelsim command to make initialization

    Modelsim question :) Yes you got my point. No modelsim shows what is fed into through the test bench and/or design module. If the signals are not initilized modelsim rather any other simulatar will show it as an "undefined" signal. There is no way to turn the signals to some high/low level...
  18. M

    Read and write bitmap file in vhdl

    bitmap to byte conversion vhdl thanks for the reply. But this is not what i intend to do. Rather I am sorry, I think I asked question which was ambiguous itself. Actually I want my test bench to read an image file and pass the pixel data to the design with other control signals. And the design...
  19. M

    Modelsim command to make initialization

    std_logic resolve undefined modelsim Hi I think this piece of code can help entity my_ff is Port (Q : in STD_LOGIC; reset : in STD_LOGIC; clk : in STD_LOGIC; D : out STD_LOGIC ); end my_ff; architecture Behavioral of my_ff is begin process (clk) begin if...
  20. M

    Read and write bitmap file in vhdl

    reading file with testbench vhdl Hi! I am tryint to write a vhdl code for downsampling of image. I have to actually write a test bench that cna can read a grayscale bitmap image and then write a downscaled version of image as a result in the bitmap format. Any help?. thanks in advance. Awais

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