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  1. blueagate

    The wrapping burst operation of AMBA bus?

    wrapping burst Does anyone can explain the wrapping burst operation of AMBA bus in detail? Thanks.
  2. blueagate

    Mixed signal verification question with Nanosim + VCS

    set_node_thresh I am debugging a mixed signal design by using Nanosim + VCS. The analog circuit is described in spice and the digital circuit is described in Verilog. A clock named A2DCLK is generated by analog circuit and feed to digital circuit. While A2DCLK rise from 0 to 3.3v, the...
  3. blueagate

    USB1.1 PHY Behavioral Model Needed

    I need a Behavioral Model of USB1.1 PHY which in Verilog or VHDL in order to test my USB code. Thanks.
  4. blueagate

    USB1.1 PHY Verilog or VHDL behavioral model needed

    usb1.1 design phy I am working a project with USB1.1, I need the USB1.1 PHY behavioral model in order to simulate the design. Please give me some information about USB1.1 PHY behavioral model. Thanks.
  5. blueagate

    How to translate the Quartus II 4.0 project to Quartus II 3.

    Since the suffix of the project name of Quartus II 4.0 is .qpf, which is .quartus in Quartus II 3.0, Quartus II 3.0 can not open .qpf file directly. When using the Archive project from the Project Menu in Quartus II 4.0, and restore in Quartus II 3.0, the hierarchy of the project will be lost...
  6. blueagate

    How to make a cpu work correctly?

    I am making a test board based MIPS, I have read some MIPS documents. I think that most documents tell me how to write the software, but I want know more about the hardware. I know that after the reset, the cpu fetch the instruction from flash/rom, this is said as bootloader. But I don't...
  7. blueagate

    How to build a evaluation FPGA board with MIPS controller?

    MIPS Board Hi, my friends, does anybody have any docs/ shchematics/ tutorial on how to built an evaluation/ prototyping FPGA board with MIPS microcontroller? We have the soft code of MIPS, download to the FPGA. Thanks.
  8. blueagate

    Help, does anyone has MIPS development board schematic?

    mips development board I will develop a MIPS board, but I am a novice with MIPS, Does anyone upload some MIPS development board schem and doucument? Thanks
  9. blueagate

    Question about scan insert using Design Compiler

    preliminary scanning ullman compiler design I want to inset scan from RTL code. The script I had written is here: analyze -f verilog top.v elaborate top some constrains here ... set_scan_configuration -style multiplexed_flip_flop crete_test_clock -period 100 -waveform {0 50} clk #clk is a...
  10. blueagate

    I want some DC scripts and RTL codes.

    Hi, friends, I am reading the book of Advanced ASIC Chip Synthesis, so I want some RTL codes and scripts to exercise. Does someone can help me, pls?
  11. blueagate

    Question about the boot of ARM.

    At the begin of the ARM code, it is necessary to set up the environment for C code, I want to know what is should be set up absolutely necessarily.
  12. blueagate

    Does anyone has the RTL code of ARM AHB-to-APB bridge?

    apb rtl I am working a design with ARM. Does anyone has the RTL code of ARM AHB-to-APB bridge? Help me, please. Thanks.
  13. blueagate

    How to simulate Altera Excalibur in Synopsys VCS?

    About Altera Excalibur Is here anybody know how to simulating Altera Excalibur in Synopsys VCS. I have read the document from Altera, but I am still feel delusively.
  14. blueagate

    Where have a free ARM IP core?

    free arm ip I need one to help my design. Thanks
  15. blueagate

    Where can I find ARM core RTL code?

    arm core rtl code I wanted to find a ARM RTL code. Thanks

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