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  1. gerade

    TSMC65 GP Dolphin LP Memory

    lp memory Hi, all, did anybody have experience using Dolphin ULP SRAM on tsmc65 GP process? we have a design that have quite a lot of SRAM(>10Mbit, most of which are dpsram) and we have to sign off the power at FF@125C and 1.1V. And we found the dominating factor is leakage from SRAM...
  2. gerade

    all_registers command

    synopsys tcl all_registers just append "> filename", then you can find them in the file. or simply use tcl to print them out
  3. gerade

    How to calculate the standard cell height?

    9 track cell heigth if lef/tf is available. height is stated inside.
  4. gerade

    Difference betwn .tf and .lef files

    tf and lef tf is from Synopsys, lef is used by cadence as tech file.
  5. gerade

    [question] minimum DC library requirement

    hi, all, I found out the requirement today, at least a DFF, an AND, an Inv and an Or gate are reqired, thanks for your attention!
  6. gerade

    [question] DRC fix in SOC Encounter

    thanks, yes, this is what I am doing know, I load the gds into icfb and fixed them interactively with calibre drc rve. Luckily there are not some many DRC errors. RGDs
  7. gerade

    [question] DRC fix in SOC Encounter

    Hi, All, it seems that SOC encounter doesn't have quite good capability to fix DRC, or? In my run, a module around 2x2 has almost 800 DRC error, and most of them are apparently not difficult to get fixed. I really go through every page of the User manual and Cadence website, and do not find...
  8. gerade

    [question] minimum DC library requirement

    Hi, I appreciate your replies very much. But I think I did not explained my question very clearly. first let's put the perfermance aside. and Latch will usually not be used if we talk about design compiler. And what I am conerning is what are the minimum number of cells that can let the...
  9. gerade

    [question] minimum DC library requirement

    Hi, Thanks for the reply. here is a short(but not accurate)the DC's minimum requirement definition. The minimum requirement is a set of cells , like DFF, Inv, Nand, Nor etc, that are the basic cells that can let the DC run synthesis, not matter the quality of the result it. If the library...
  10. gerade

    [question] minimum DC library requirement

    Hi, Guys, we are going to make a standard cell library ourselves for DC synthesis, and come into a question. As we don't want build complex gates like AOI or AIO etc, we want to know what is the minimum requred standard cell set for Design C0mpiler. I searched through the DC manual and...
  11. gerade

    How to build a memory hard macro for Astro

    usually the IP supplier will provide you the physical view like LEF and timing view .lib. if you customize the IP yourself, you need to create these views yourself........then it is a long story.
  12. gerade

    What different are I2C and SPI?

    Hi, I have another question here regarding IIC. why IIC is used quite often in a lot of multimedia products like HDTV?? RDS and TNX
  13. gerade

    constraints for Xilinx ISE , useful or not?

    how are constraints generated in ise Hi, the Devices I used is Virtex II xc2v2000 and xc2v3000, and the logic design around 600 K gates. The clock fed in is around 80Mhz and the main system clock inside is 80/3 MHz. the PC I use is 3GHz + 2G memoried. I ran into quite a lot of trouble to set...
  14. gerade

    Difference between FPGA and ASIC

    asic design global reset Hi, FLEXcertifydll and all, how to make a glitch-free clock gating?
  15. gerade

    constraints for Xilinx ISE , useful or not?

    xilinx related clock dividers constraint Hi, all, in the past months, I have been using Xilinx FPGA to built prototypes. and from my experience with the design flow and observation, I met a "conclusion" that detailed contraints for the synplify-pro && Xilinx iSE flow will help to get a better...
  16. gerade

    Difference between RTL and behavioral code

    Re: RTL Vs Behavioral Hi, all, is there any book or website regarding behavioral modelling available? TNX in advances. Gerade
  17. gerade

    [question] clock gating cell

    gating cell can anyone give me a hand?
  18. gerade

    [question] clock gating cell

    clock_gating rtl Hi, All, Currently we encounter a problem with clock gating cell. Synplify always adds an AND gate behind the latch, the inputs to the AND are a global clock(usually with iso suffix) and the clock generated from the latch. the VHDL is shown below, library ieee; use...
  19. gerade

    [question] which tool for SOC top level integration

    soc top integration Hi, *, integration is a quite tedious step in SOC flow, and manual work will be certainly slow and incapable. I used a companay inhouse tool, and it is quite dumm. which tools do you guys use, and which one will be the best?? TNX in advance! Best Regards Gerade
  20. gerade

    how to replace F/F without RESET using F/F with RESET?

    yes I prefer that 2, the same time, even change RTL is not possible or permitted, still you can pass formal verification by tie reset to 1. regards

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