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  1. gerade

    TSMC65 GP Dolphin LP Memory

    lp memory Hi, all, did anybody have experience using Dolphin ULP SRAM on tsmc65 GP process? we have a design that have quite a lot of SRAM(>10Mbit, most of which are dpsram) and we have to sign off the power at FF@125C and 1.1V. And we found the dominating factor is leakage from SRAM...
  2. gerade

    [question] DRC fix in SOC Encounter

    Hi, All, it seems that SOC encounter doesn't have quite good capability to fix DRC, or? In my run, a module around 2x2 has almost 800 DRC error, and most of them are apparently not difficult to get fixed. I really go through every page of the User manual and Cadence website, and do not find...
  3. gerade

    [question] minimum DC library requirement

    Hi, Guys, we are going to make a standard cell library ourselves for DC synthesis, and come into a question. As we don't want build complex gates like AOI or AIO etc, we want to know what is the minimum requred standard cell set for Design C0mpiler. I searched through the DC manual and...
  4. gerade

    constraints for Xilinx ISE , useful or not?

    xilinx related clock dividers constraint Hi, all, in the past months, I have been using Xilinx FPGA to built prototypes. and from my experience with the design flow and observation, I met a "conclusion" that detailed contraints for the synplify-pro && Xilinx iSE flow will help to get a better...
  5. gerade

    [question] clock gating cell

    clock_gating rtl Hi, All, Currently we encounter a problem with clock gating cell. Synplify always adds an AND gate behind the latch, the inputs to the AND are a global clock(usually with iso suffix) and the clock generated from the latch. the VHDL is shown below, library ieee; use...
  6. gerade

    [question] which tool for SOC top level integration

    soc top integration Hi, *, integration is a quite tedious step in SOC flow, and manual work will be certainly slow and incapable. I used a companay inhouse tool, and it is quite dumm. which tools do you guys use, and which one will be the best?? TNX in advance! Best Regards Gerade
  7. gerade

    question about DRAM cell capacitor from a digital designer

    Hi, Guys and Gals, How much is capacitance of the DRAM cell capacitor for .18 or .11 about? nx10fF? or? just want to get a rough idea. thanks in advance! Gerade
  8. gerade

    synchronization cross clk domains

    Hi, Guys, my task is to design a module, that has 2 different clk domain, one clk may vary from 500k to 30 Mhz,for different applications. The other clk is around 30 MHz. any one can help me pls? thanks for your attention and time! Best Regards
  9. gerade

    help, some brief for division?

    hi, guys, in my project, I am designing an MDU. and this mdu doesn't have very high requirement for timing, but for area. actually it is just a add/substract and 1bit shift per machine cycle. that means 16/8 division will take abut 9 clock cycle. but I am so familiar with the algorithm...
  10. gerade

    help: how to download suse "ISO version"?

    help how to download suse, is there any ISO, I tried a lot ftp, but never find ISO. what i found is just some big diretory tree, and don't know how to deal with them. :( any idea or advice. TNX
  11. gerade

    question about full customer design flow

    how many steps will you carry out you design, and in different step which tool will you use then. what i learned through, draw layout with cadence, LVS DRC with calibre or dracula circuit input with composer circuit simulation with hspice logic simulation with nc or modelsim what else is...
  12. gerade

    it seems that specman will double verificationer's load.

    you have to model the design yourself. Besides, you still have to write stimuli. it seems quite much for the guy who is doing verification. so what is the advantage for such in language then?

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