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Most of the material discussing antenna rule says that
metal antenna ratio (AR) is not cumulative (e.g. just count M2 alone, not M2 and M1 together).
Is this because the gate leakage discharges the metal which is already fabricated?
Maybe for more advanced technology...
I'm wondering where the via location should be on the power line, considering resistance, current density and fabrication performance.
Take the following picture as an example.
Which one approach do you prefer? Any reason?
Thank you very much for your feedback :grin:
I know the function to do rotate by bindkey "leRotateCB()"
How about flip MX and MY by bindkey after clicking move or copy?
I know Key F3 can do the operation, and then click MX/MY buttons
Thanks a lot
What is the function of tuning fork in flash memory IC layout?
Is it used for positioning the core array?
Is it allowed to place transistors under tuning fork?
Thank you for your sharing in advance.
I am now studying convergency issue in Hspice.
As all of you know, convergence is defined as the ability to obtain a solution
from a set of circuit equations within a given tolerance criteria.
Could anyone explain the above mentioned definition using a simple example?
I want to design an error amplifier for PWM dc-dc boost converter.
It only drives capacitive load so I think OTA is needed.
(1) How much should the gain be?
How does the gain affect the performance? Line regulation? Load regulation?
Or something else?
(2) The frequency of the...
I'm simulating a boost converter in DCM.
The inductor current is supposed to decrease until zero
during the switch is OFF.
However, from my simulation results, the inductor current
drops to -ve values. Why come?? How to solve such problem??
L = 400uH
C = 100nF
R = 3.3k
SW is large...
I have a question regarding charge pump.
Vout of charge pump = (n+1) Vdd where n is the # of stages
Q1. In practice, Vout never reach (n+1)Vdd. What are the causes?
Q2. When the # of stages increases, Vout does not increase PROPORTIONALLY. Why??
Your comment is highly...
Just interested to know:
Why is the minimum drawn width of top-level metal always larger than that of bottom-level?
For example, to pass DRC:
Wmin of M5 = 0.44um
Wmin of M1 = 0.26um
Thanks for your answering in advance.
In the old days, metal was used as the gate of MOS.
But now, polysilicon is used.
Metal has a lower resistivity than polysilicon.
What is the reason for using polysilicon now?
I think of a few reason:
1. Polysilicon is easier to stick to silicon oxide.
2. Polysilicon can achieve...
I am designing a boost converter.
From the simulation, the efficiency decreases as the duty cycle increases.
Is this because more power is consumed in the inductor-NMOS path as the NMOS ON time (duty cycle) increases??
Your comment is highly appreciated ~
concwentration in p+
I'm now studying a course related to semiconductor device.
As far as I know, the doping concentration of:
P+ = 10^18 / cm3
P = 10^15 / cm3
How about P- ?? Any information about the doping concentration of P- ??
Is the doping concentration of P- less than...
Is there any paper or document related to adjustable reference voltage design?
For example, I want a supply-independent reference voltage which can be tuned using control signal (digital or analog).
Is it possible to implement such kind of circuit?
Your comment and guidance are...