Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. kib

    VGA display on a bigger monitor

    vertical counter logic is wrong check this vhdl code for vga sync generation (example code from rapid prototyping of digital systems) LIBRARY IEEE; USE IEEE.STD_LOGIC_1164.ALL; USE IEEE.STD_LOGIC_ARITH.ALL; USE IEEE.STD_LOGIC_UNSIGNED.ALL; ENTITY VGA_SYNC IS PORT( clock_25MHz, red, green...
  2. kib

    Bypass Capacitors at DIGITAL IC pins

    Well explained in Wiki https://en.wikipedia.org/wiki/Decoupling_capacitor
  3. kib

    Generation of minimal polynomials

    Check this https://www.cs.umbc.edu/~lomonaco/f97/442/Peterson_Table.html
  4. kib

    SystemVerilog mode for emac

    check this https://groups.google.com/group/avm-users/browse_thread/thread/a8a2c0bdde186740 regards kib
  5. kib

    [SOLVED] Pic 16f876a Pure Sinewave inverter

    what is pwm inverter hello taner, can you also share the pcb layout diagram. thanks kib
  6. kib

    synchronous reset (verilog)

    try this code assign temp = rtl8305_mtxen ? (~toggle_bit) : 1'b0; always @(posedge sys_clk_25m) begin if(!syn_rst_n) toggle_bit <= 1'b0; else begin toggle_bit <= temp; end
  7. kib

    Asynchronous FIFO design for the video controller

    calculate video fifo depth fifo depth will depend on how frequent you read if you read every alternate clocks then a fifo depth of 256 should be sufficient for you. check this link to know more about fifo depth calculation https://www.asic-world.com/tidbits/fifo_depth.html
  8. kib

    has anyone used ADV7123 video dac

    Download the application notes from here **broken link removed**
  9. kib

    what's the different between Logic cell and CLB?

    1 LUT = 1.125LC's Check this answer from Peter Alfke **broken link removed**
  10. kib

    Help me design a 100W power amplifier

    Re: amplifier are you looking for audio power amplifier. then www.diyaudio.com regards kib
  11. kib

    SATA PHY Chip for FPGA

    sata phy Actel also has SATA PHY devices check this http://www.atmel.com/dyn/products/devices.asp?family_id=677#1511 regards kib
  12. kib

    How to install Xilinx ISE on Linux?

    install ise on linux i have successfully installed ISE8.2 on slackware 11.0 run the script setup located in ise82i\platform\lin folder of the DVD regards kib
  13. kib

    Clock division by an non integer number using VHDL

    counter division vhdl Why do you require a divide by 2.5 circuit. Why not directly use a divide by 5 cicuit to get 1Hz from 5Hz. check this regards kib
  14. kib

    Clocks for generating the DQS strobe signal in DDR RTL

    Re: clocks in DDR core There are 2 ways to clock a DDR flop's Below image shows the same I have normally used the inverter inside the IOB to invert the clock and has worked for me without any problem. I have target tested my design upto clock speed of 166MHz. Regards kib[/img]
  15. kib

    Looking for Protel 2004 for Linux

    Re: Protel2004 For LINUX Protel2004 does not come in linux version. But you should be able to run it under Wine.
  16. kib


    processor in verilog why not picoblaze. it is downloadable from xilinx free of cost regards kib
  17. kib

    Regarding 16-bit multiplier

    below is a 8-bit shift and add multiplier code in vhdl. u can take it as reference and design a 16-bit multiplier. --------------------------------------------------------------------------- -- The multiplier --------------------------------------------------------------------------- entity...
  18. kib

    Looking for VHDL code for receiver UART

    Re: VHDL-UART-FPGA this is code for uart receive but in verilog from xilinx app note module rcvr (dout,data_ready,framing_error,parity_error,rxd,clk16x,rst,rdn) ; input rxd ; input clk16x ; input rst ; input rdn ; output [7:0] dout ; output data_ready ; output framing_error ; output...

Part and Inventory Search