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  1. F

    help:::about PLI and VPI problem!!!

    I want to run simulation with NC_verilog. during sim i want to dump fsdb file and call some MyPLI function and task. My problem is : >>ncverilog -f run.f after type the above command, the nc will load the default pli&vpi lib, which is libvpi.dll and libpli.dll. Now i have two pli.dll one is...
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    help :need one CPU model!

    i want to need one risc cpu behavioral model to verificate my design, maybe it could be written with Systemc. where i could find it? thank all.
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    to wadaye (about asic design)

    pls give some answer! Now i am take part in one prj about pci ip desgin. i have finished the FPGA verification. i am familiar with the FPGA design flow. but i am going to start the ASIC desgin flow later. so i want you to give me detail desgin flow. i have read the book advaned chip...
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    i want to design a pci interface

    but where i could find one PCI module for test? thx
  5. F

    want to learn asic, how to begin

    learn asic now i am finishing one design verification on FPGA. i want to go on with this ASIC design. somebody could tell me, how to begin it!? what is the design flow? which tool is used? thx! green hand
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    help me: where is Specman s/w?

    When i am learning the verification method according to "Writing testbench", i know E language. so i want to learn it and use it to write some simple program. but i cann't find the Specman anywhere. So anyone could help me. i only want to learn it. thx all.
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    about soft radio - any materials?

    about soft radio anyone could provide some material it! it is a new topic. i could find more material in web.

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