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  1. R

    Confuse about set_false_path & set_disable_timing

    Sarath, your explanation is not clear. I'm still have confuse about them. set_false_path is use for a pair of start & end point. But set_disable just apply for 1 point in timing path. Is it correct?
  2. R

    Host setting in DMSA

    Hello guys, I've just built DMSA env to fix timing in PT. But after set host, I can't create session. I use this command: set_host_options -num_processes 2 \ -submit_command "/tools/cad/synopsys/J_version/pts_J-2014.06-SP3/bin/pt_shell" current_session -all Error: Insufficient hosts online...
  3. R

    Summary timing path in PT

    >> so, I think you need tcl/perl/... script, it's not related to PT >> go to learn tcl/perl and you can create summary with what format you want. Yes, you are correct. But I'm beginner, need time to master scripting. And my boss put deadline for this task. So, I can't finish in short time like this.
  4. R

    Summary timing path in PT

    @Oratie, report_qor can do. But I mean need to summarize from an existed timing report. So, I need a script to do this.
  5. R

    Summary timing path in PT

    Hi all, I need your help about summary tools script. I must to summary timing path according to slack & path_group from a timing report (get by report_timing command). For example: I have a timing report file is : tim.rep I want to summary as below format: No. Path_Group WNS TNS...
  6. R

    Negative delay in Primetime

    Don't get me wrong ads.. I mean when I analyze timing report from pt, some cells/nets have a negative delay in the report. But I dont know where they come from. Maybe the threshold slew of output pin is smaller than input pin.
  7. R

    Negative delay in Primetime

    Hi everyone, I have a question about negative cell delay in pt. Could you show mw where does the negative delay come from? BR.
  8. R

    Confuse about set_false_path & set_disable_timing

    Hi everyone, What is the difference points between set_false_path & set_disable_timing? When should we use which suitable command? BR,
  9. R

    Clock gating check in STA

    Hi all, I have 1 confuse point about clock gating check. Could you please explain for me: - What is clock gating? - Why do we need to use gating? - In my timing report from Primetime, Where does clock_gating_setup_time come from? BR.
  10. R

    what if skew required not matched?

    When you can MET the timing and achieve other requirement, this means your clock skew is not problems. Because if your skew is so bad, you can'e met the timing.
  11. R

    Timing borrowing definition

    Hi guys, I'm so confuse about "borrowing timing". So, cuold you explain simplest about it for me? It's better if you have related acrticle about it. BR.
  12. R

    How to decide which cell has to be resized to fix setup violation?

    Does this means you want to fix this path manually? If yes, please choose upsize or swap Vth of cells which have big delay or big fanout. Dont forget to check margin of HOLD path through these cells before you choose them.
  13. R

    Confuse about the process

    Hi all, Today, my supporter ask me 1 question. But I'm not sure how to answer excectly. This is the question: "What difference did you see moving from 45nm to 28nm in: - Timing point of view - Layout view " Please give me your opinion about it. BR, Wang.
  14. R

    [SI] Xtalk SI affection

    Hello guys, I confuse about Xtalk affection. How many types of SI effect to timing? And how to avoid and fix the timing violation caused by SI? BR.
  15. R

    Set pin load constraint

    ia anyone has other idea? please teach me :(
  16. R

    confuse about yield in PD point of view

    hi all, I have a question about yield. what does it mean if someone say that"the yeild is poor"?
  17. R

    Set pin load constraint

    hi erikl, thanks for reply. 1) fanout is important. But how about clock definition? 2) I'm sorry that I cant catch up yr mean. could you explain more? 3) my friends said that we should choose HOLD. Because, we can fix SETUP by relax some margin (Ex: clock uncertainty, clock cycle...), but HOLD...
  18. R

    Set pin load constraint

    Hello guys, My friend ask me 3 questions, but I'm not sure to answer him. 1) What are the important constraints in a SDC file? why? 2) What are pin load constraints? why we use it? 3) we need to TAPEOUT in 4 days & we have both SETUP & HOLD violations – which one we fix first & why? Please...

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