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    How to display characters on a vga console?

    vga console i have made a 640x480 VGA controller in verilog. as a test i generated red green and blue lines on a monitor. but now i want to display alphanumeric characters. i have some idea about using a character buffer and a font ROM. but can someone please tell me how i should do it?
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    can i unplug the vga cable while windows is running

    monitor only turns on when unplug vga actually im designing a vga controller on an FPGA and for that i have to check the design again and again. for that i have to first disconnect from my dialup connection and then shut down my pc and then connect the monitor to the FPGA kit. i was just...
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    signed addition in verilog

    verilog addition im doing a project in which i need to add two signed numbers. how can i check for underflow and overflow? module stimulus; reg signed [7:0] a,b; wire signed [7:0] c; signed_adder my_adder(a,b,c); initial begin $monitor($time, " a = %d, b = %d, c = %d", a, b, c); end...
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    can somebody help me understand this piece of code of an FIR

    module fir_srg (clk, x, y); //----> Interface input clk; input [3:0] x; output [3:0] y; reg [3:0] y; // Tapped delay line array of bytes reg [3:0] tap0, tap1, tap2, tap3; // For bit access use single vectors in Verilog always @(posedge clk) //----> Behavioral Style...
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    Help me connect 25MHz clock to FPGA and then get 400Hz clock

    the problem is that i have written the code for my design and i have performed the functional simulation. now i want to target an XC2S50 for my design. the thing is that i havent done this kind of a thing before. i have Xilinx ISE 6.2 and i do know how to run it. my design requires an input...
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    How to produce a synthesizable delay

    i have a problem where data from one module has to be given to another module but with a delay. in simulation with modelsim delays can be easily generated by #<amount of delay> but how can i produce a synthesizable delay. lets say i want an equivalent of #30 the time is in nanoseconds and...
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    how can i detect the positive edge of a signal in verilog?

    find positive edge of signal how can i detect the positive edge of a signal using an if statement in verilog. if i had to detect the level of a signal i would use if(signal) begin ........ ........ end but what if i want to detect only the positive edge of a signal??? my limited...
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    How to configure UART to receive 4-bit words and transmit 7-bit ones

    hi everybody, im a beginner in verilog and i have only made a few small designs. as a first attempt to start with new designs i was thinking of making a UART. i found a nice looking UART at https://www.opencores.com/projects.cgi/web/sasc/overview the author says that the UART transmit and...

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