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  1. S

    How does clock latency affect setup and hold time?

    Clock latency just means how much time it took for your clock signal to reach from clock generation point to sink. Ideally, the latency to all the sinks from a clock should be same, meaning all registers are receiving clocks at the same time. However, that is not the case, and hence we add...
  2. S

    Multi voltage Design Issues

    A chip can be in different power states like: sleep mode, hibernating mode, stand by mode, shutdown mode etc. Right? In different power modes, different instances will be running on different voltages. For example an instance may be running at 1 volt in normal mode while in sleep mode it runs on...
  3. S

    Multi voltage Design Issues

    Thanks for the reply. I do not have any issues related to setup time or hold time. The design is a low power based design where in normal mode the design runs on full power while on low power mode we bring the voltage down for some power domains in the design. The way it is done is done is...
  4. S

    Multi voltage Design Issues

    Hi, I need some clarification on multi voltage design. Lets say a particular instance in my design is running on two different voltages. In normal mode it runs on 1.2 volts and in special mode it runs on 0.8Volts. How is that done? I mean every cell in that instance will be linked to a library...
  5. S

    Fixing critical Hold violation

    Yes, it will but downsizing is always a better approach as it will not add extra buffers in the design and according to my experience the effect of downsizing on setup is lesser than adding buffers. Anyway the hold will affect setup violations if the setup path has very little slack. ----------...
  6. S

    Setup and hold time calculations

    Decreasing size of capture may help in meeting hold violations...but not setup.
  7. S

    Arithmetic and Logic Unit (ALU) design / data-gating

    I dont think there is a need for gating since gating would be helpful only if there is a clock involved. In that case, dynamic power consumption becomes the issue and a gated logic would be helpful. So, I think your point is correct.
  8. S

    [Hard] What is the pros/cons of more stages pipelining

    Yeah.. and what about pipelining hazards..? I mean will they increase or not..?
  9. S

    [Hard] What is the pros/cons of more stages pipelining

    More pipelining means more buffers insertion. Thus hardware cost increases.
  10. S

    reg t output setup fixing

    Check the path if there are too many buffers in that path. If yes, also check how many nets they are being connected to. If there are unnecessary buffers that are not affecting other paths and if they are not affecting hold violations in that path, you may try to remove them.
  11. S

    Congestion analysis in IC Compiler

    In IC Compiler, there are three congestion maps namely: Placement congestion, Global Route congestion and Detail Route congestion. Whats the difference between them ? Thanks
  12. S

    [Layout] Clock Tree routing

    I have a doubt regarding layers. It is said that all the cells and macros lie on base layer. Now, by definition, macros are like black boxes and internally all the routing is already done in it. Now my question is how can a macro lie entirely on base layer when there is metal routing done...
  13. S

    [Layout] Clock Tree routing

    It is generally preferable that the lower layers are thin because the signal routes needn't withstand high current. Moreover if the layers are thick, than more spacing will be required according to minimum spacing rule. Thus lesser no. of metal tracks will be available for routing. ----------...
  14. S

    [Layout] Clock Tree routing

    @pavanks: I'm not a pro in vlsi domain. I'm myself in the learning phase. So I might go wrong at some places. But, if high fanout is not a constraint, then why top layer is being reserved for clocks because in my knowledge the only reason we use top layers is high current conductivity...Plz...
  15. S

    [Layout] Clock Tree routing

    Clock tree is always given more preference than other signals in terms of routing because maximum switching takes place in these nets and clock needs to be propagated to all the cells. Thus, they need to have minimum IR drop and more current capacity. Thus top layers(just below power nets) are...
  16. S

    why insert filler cells into empty space?

    Its opening in my case..anyway the image is below: Image:
  17. S

    why insert filler cells into empty space?

    LVS: Check wikipedia page. Its given very clearly over there. https://en.wikipedia.org/wiki/Layout_Versus_Schematic Timing Closure: By timing closure it means that all the timing criteria like setup and hold constraints are satisfied and the design works fine at the specified frequency thats...
  18. S

    why insert filler cells into empty space?

    GBF Cells are Gate Array Backfill cells. I heard a similar explanation for these cells, so thats why i asked..:)
  19. S

    why insert filler cells into empty space?

    So, does that mean filler cells play no role in latchup prevention? ---------- Post added at 11:57 ---------- Previous post was at 11:52 ---------- another question i had about spare cells is...are spare cells and GBF cells same or different? thanx

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