Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. J

    [SOLVED] The speed of standard logic cell is not enough

    Hi, I meet a problem, the speed of standard logic cell is not enough. I wish to know the how much custom cell can faster than standard logic cell? Please help me, thanks. John
  2. J

    make a choice of memory power in SOC

    Here has 2 memory device A and B: The active current of A is 10 mA, B is 20 mA; and leakage current of A is 20 uA, B is 10 uA. For a hand on SOC design, like cellphone processor chip, which memory device is better choice? A or B? Please help me.
  3. J

    The power of 28nm SRAM with 256 X 32 X8 ?

    Hi, I need the power of 28nm process SRAM with configuration 256 X 32 X 8. This is urgent. Could any one help me ? Any feb's data is ok. Thanks a lot.
  4. J

    The power of sense amplifier is what percentage of SOC embedded memory read power?

    Hi all, I have searched the sense amplifier related information of SOC embedded memory. Could anyone told me the power of sense amplifier is what percentage of SOC embedded memory read power? Thanks a lot. John
  5. J

    sense amplifier is what percentage of SRAM memory in 28nm process

    Hi, Does any one told me the sense amplifier is what percentage of SRAM memory in 28nm process? I need 128*32 and 256*32 memory macro information. Thanks a lot. John
  6. J

    28nm process standard NAND cell characteristic

    Hi, I need the characteristic of 28nm process standard NAND cell. Include AC power, input capacitance, intrinsic delay, and Kload. Please help me. Any FEB's data is ok. John
  7. J

    28nm SRAM MOS capacitance

    Hi, I need the 28nm MOS capacitance (gate to ground and drain to ground) value of 6T SRAM cell to calculate power. Any FEB's data is fine. Please help me. Thanks a lot. John
  8. J

    4T2R SRAM compare with 6T SRAM

    Hi All, Could you tell me the difference with 4T2R SRAM and 6T SRAM? I need the advantage and disavantage of both. Thanks a lot. John
  9. J

    Why the capacitance of 180nm is the same as 32nm?

    Hi all, I find out the data following: 180nm process : the capacitance of M1 : 0.2fF/um. 32nm process : the capacitance of M1 : 0.2fF/um. But the metal 1 line area of 32nm process should smaller much than 180nm process. Why their capacitance is almost the same...
  10. J

    Other logic circuit has same feature to CMOS ?

    Hi, Has there other logic circuits with same features to CMOS ? Like low power and fast speed. Thanks for help. John
  11. J

    metal line width and running speed racing

    Hi, On metal line has 700um long, 0.25um width, for 0.2fF/1um, the capacitance of the metal line is 0.2*700=140fF. If the metal line need run up to 1GHz. The peak current is V/R, R=t/5C=1ns/5*140fF=1.4k. I=V/R=1.8/1.4K=1.28mA. But the metal width is 0.25um=> only can run 250uA. So the...
  12. J

    max current in different layer at 45 nm process

    current carrying capacity in different layer at 45 nm process Hi All, I estimate one plan now. I need current carrying capacity in M1 M2 M3 M4 with 140nm width metal line at 45 nm process. Could any one help me ? Thanks. John
  13. J

    Apple A7 metal layers?

    Hi All, Does any one know how many metal layers Apple A7 used? Thanks.
  14. J

    System verification information needed

    Hi All, I have experience with block simulation in digital design. I wish to learn large system verification including hardware/software co-sim. Could someone give the completed example or book of it ? Thanks a lot. Brs, John
  15. J

    180nm/40nm/28nm SRAM capacitance?

    Hi, I need the capacitance (MOS capacitance , the node connect to bit line ) value of 6T SRAM cell to calculate power. The process 180/40/28nm of any FEB is fine. Please help me. Thanks a lot. John
  16. J

    0.18um SRAM macro information

    Hi All, I need the 0.18um SRAM's active power(mA) and area(mm^2) as following : (1) 4096X32 bits run at 50Mhz and multiplexer sets to 16. (2) 32768X32 bits run at 50Mhz and multiplexer sets to 16. Please help me to get the related information. Any Feb's data is good. John
  17. J

    0.18um SRAM Cell size

    Hi All, I find out the size of 90nm SRAM cell is 0.575umX2.05um. But I can't find of 0.18um SRAM Cell size. Please help me for 0.18um SRAM Cell size. Any FEB's data is fine. Thanks a lot. John
  18. J

    0.18um SRAM transistor RC value with out sense amplifier.

    0.18um SRAM transistor RC value Hi all, I need to know the Resistor and Capacitor value of 0.18um SRAM transistor to calculate the speed. Any feb's data is fine. Please tell me. Thanks. John
  19. J

    SRAM write timing request

    Hi all, As we know, due to large RC time constant of SRAM bit line, so it need sense amplifier for read mechanics. Because the read bit line and write bit line is the same line of SRAM, so their RC time constant is the same. How could write timing can fast as read timing? Please help...
  20. J

    Layout size question in standand cell.

    Dear All, The standand cell information is following: .subckt BUFX1 Y A X_g0 Y net7 inv pl=0.18u pw=1.92u nl=0.18u nw=1.3u X_g1 net7 A inv pl=0.18u pw=0.71u nl=0.18u nw=0.47u .ends BUFX1 The cell size is 0.18*(1.92+1.3+0.71+0.47)=0.18um*4.4um But the data sheet shows the standand cell size...

Part and Inventory Search

Top