Welcome to EDAboard.com

Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.

Search results

  1. neetinsingh

    clock uncertainty vs clock jitter

    Following link would be of great help..... -neetin
  2. neetinsingh

    I have a question - (Interview question)

    To check whether there will a glitch or not we will perform the clock gating timing check on the select line of mux.
  3. neetinsingh

    DFT explanation basic nomenclature

    Re: DFT explanation What is difference between, Test_mode (TM) pin and Scan_Enable pin? Test_mode pin is use to put SOC/ASIC into TEST MODE or Functional mode. There are various test modes in DFT like ICTECT, IDDQ, IO BIST , AC/DC TEST, MBIST, JTAG etc. Scan_enable is only significant in the...
  4. neetinsingh

    fan-out fixing with higher drivver cell

    Re: fan out fixing ???? thanks hung n ebuddy :D
  5. neetinsingh

    transition time reduction???

    hey hung....thanks a ton.....i really appreciate ur effort for putting thing in a simple way....
  6. neetinsingh

    transition time reduction???

    can u be bit elaborative.....i didnt get ur point....
  7. neetinsingh

    fan-out fixing with higher drivver cell

    fan out fixing ???? how fanout is met by replacing the cell with a higher driver cell?
  8. neetinsingh

    transition time reduction???

    How transition time get reduced after inserting buffer at the driving pin of the cell?
  9. neetinsingh

    Read Margin violation of RAm

    Hi I am doing top level MBIST pattern generation and simulation for a modlue . While pattern simulation i am gettin Read margine violation for the RAM but my simulation is passing. I think it might be due to the clock frequency going in to the RAM. I want to know what is the effect of this...
  10. neetinsingh

    TLM (TAP Linking Module)

    tap linking module Hi Can any body upload some material explaining the funtioning of TLM used in JTAG.
  11. neetinsingh

    How to trace UO faults in Mentor's DFTVisualizer

    dftvisualizer hi i had currently started working on the Mentors Fastscan and its supporting tool. can anyone tell how to trace the cause of UO(unobservable fault). should i forwrd trace it or backtrace it????????????
  12. neetinsingh

    how to design an odd or fractional frequency divider?

    how to design an odd or fractional frequency divider having 50% duty cycle??? divide by 1.5 , 2.5 , 3,5 and divide by 3 , 5 , 7
  13. neetinsingh

    combinatorial ckt in clock path

    It will add clock skew which cuases timing issue and also cause controlabilty issue in DFT implementation........
  14. neetinsingh

    software reset & hardware reset???????

    wht is software reset and hardware reset???????????:D:D:D
  15. neetinsingh

    Address scarmbling?????

    hi If possible can u please upload the paper u r talking about............... regards neetinsingh
  16. neetinsingh

    Address scarmbling?????

    What is address scrambling in memories???????
  17. neetinsingh

    Data retention test...........

    What is data retention test in memories and why its being performend?????????
  18. neetinsingh

    embedded memory and embedded core??????????

    what is embedded memory and embedded core in a SoC????////
  19. neetinsingh

    analog ASIC & digital ASIC

    is there anything like analog asic and digital asic???? if yes than whts the difference.............
  20. neetinsingh

    Books for ADC and DAC..?

    hi go to following link u will find a book on adc regards neetinsingh

Part and Inventory Search