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modelsim + disable dumping
Let me suggest a solution.
I have learned that Novas (certainly latest version Debussy and possibly Verdi) does support extraction of sub-signal waveform from a large waveform log.
The trick is it is a FSDB formatted file. Luckily, Novas has kindly provided...
Ya, as pointed by Aji, I have posted a subject "Seeking TRUTH: Specman Elite" at Janick Bergeron's Verification Guild. Got some replies, even 1 from Verisity representative.
Now, about support for Specman Elite, I believe these companies support/back Specman Elite...
different specman execution phases
I love Specman. It is very very much like VHDL, with few but powerful cosmetics.
Given the choice, I will be pick Specman E language, which is adopted as IEEE verification language. Do a search and you will find the official page. Vera? I think it is...
in addition to the above posting, please visit the site
It is about Writing Testbenches: HDL verification by Janick Bergeron.
In this post, there are materials on verification tools. I think it could be more precise than my descripton give above.
equivalence checking <=> model checking.
it finds its application in comparing RTL vs RTL, RTL vs gate, gate vs gate after design changes (or more kinkily known as ECO, engineering change order). It helps designers by ensuring a minor design changes do not modify other modules's functionality...
i don't think so.
SystemC will be for System level modelling (transactional level model) and synthesis (Forte Design's Cynthesizer, Coware, Mentor Graphics). Sounds like to the evolution path that VHDL went through. as you know, VHDL had initially designed for simulation.
modelsim disable warning
solution 1 - editing MODELSIM initialisation file
go to Modelsim installation, then you should find "modelsim.ini" under the
path <install_path>. First, to edit this file, you need to make it write enable; turn remove the READ-only protection.
vsim foreign attribut
-----------snippet for SYSTEM-C
ModelSim 6.0 supports SystemC on Windows. sccom uses MinGW gcc 3.2.3 for compiling the SystemC source code. C-Debug is supported on Windows with MinGW gdb 6.0.
--------- full snippet
Release Notes For ModelSim SE/PE/LE 6.0 Beta...
Can you tell us where these documents are taken from?
If these are the user documents supplied by the Vera, then tell us! It is useless to us. We have it installed already.
tutorial on synapticad
I would like to who ( in this forum ) uses SynaptiCAD products.
I am using its TestBencher Pro to automate my VHDL testbench. However, I could not simulate the project (using the tutorial example) in ModelSIM from Testbencher Pro (version 9.0p). Am i missing...
free download presentations (no points deducted!)
www.cic.edu.tw/information/info_seminar/2002_design_tool_workshop/ pdf/xxxxx... (you know what I meant!)
I have some question regarding Synopsys VERA.
How do I execute VERA Testbench? Do I need only software VERA 5.1.1 from Synopsys FTP in order to execute VERA coded testbench? Or, I will need to install Synopsys VCS version xx and VERA 5.1.1 software. please clarify.