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  1. S

    How to extract signal to start or stop dumping

    modelsim + disable dumping Hello. Let me suggest a solution. I have learned that Novas (certainly latest version Debussy and possibly Verdi) does support extraction of sub-signal waveform from a large waveform log. The trick is it is a FSDB formatted file. Luckily, Novas has kindly provided...
  2. S

    Which one is better Vera or Specman?

    vera e-specman Hello Again: Ya, as pointed by Aji, I have posted a subject "Seeking TRUTH: Specman Elite" at Janick Bergeron's Verification Guild. Got some replies, even 1 from Verisity representative. Now, about support for Specman Elite, I believe these companies support/back Specman Elite...
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    Which one is better Vera or Specman?

    different specman execution phases I love Specman. It is very very much like VHDL, with few but powerful cosmetics. Given the choice, I will be pick Specman E language, which is adopted as IEEE verification language. Do a search and you will find the official page. Vera? I think it is...
  4. S

    Baseline LDV5 VS ISR Vs QSR

    how about "overlay" of cadence software? is this patch to the baseline installed software? please comment. saho
  5. S

    What's the best way to do Regression Testing?

    hello. can someone post example of scripts for reference and coding style. saho
  6. S

    Assertion based methodology and tool user manual

    hello. I am interested in learning and using assertion (PSL, SystemVerilog) on my next verification project. Can you share with me your success story (not from tool vendor!)
  7. S

    What is Equivalence Checking?

    in addition to the above posting, please visit the site It is about Writing Testbenches: HDL verification by Janick Bergeron. In this post, there are materials on verification tools. I think it could be more precise than my descripton give above. happy learning.
  8. S

    What is Equivalence Checking?

    equivalence checking <=> model checking. it finds its application in comparing RTL vs RTL, RTL vs gate, gate vs gate after design changes (or more kinkily known as ECO, engineering change order). It helps designers by ensuring a minor design changes do not modify other modules's functionality...
  9. S

    SystemC will die? Why, can anybody give an explain?

    i don't think so. SystemC will be for System level modelling (transactional level model) and synthesis (Forte Design's Cynthesizer, Coware, Mentor Graphics). Sounds like to the evolution path that VHDL went through. as you know, VHDL had initially designed for simulation. SystemC simulation...
  10. S

    [REQ] User manual for @HDL, RealIntent, Cadence PSL tool

    Any user manual, tutorial, training on using these PSL (property based language) tool from companies : @HDL, Safelogic, Cadence Incisive, RealIntent.
  11. S

    [REQ]TransEDA VN-SPEC user manual

    TransEDA VN-SPEC --- specification based verification tool. any user manual?
  12. S

    how to suppress warning in modelsim

    modelsim disable warning hello. solution 1 - editing MODELSIM initialisation file ---------- go to Modelsim installation, then you should find "modelsim.ini" under the path <install_path>. First, to edit this file, you need to make it write enable; turn remove the READ-only protection. ...
  13. S

    why Verdi/0-In Check/specman not NT-platform ?

    vsim foreign attribut -----------snippet for SYSTEM-C ModelSim 6.0 supports SystemC on Windows. sccom uses MinGW gcc 3.2.3 for compiling the SystemC source code. C-Debug is supported on Windows with MinGW gdb 6.0. --------- full snippet Release Notes For ModelSim SE/PE/LE 6.0 Beta...
  14. S

    Links to Specman Elite tutorials

    specman book See my post: Design Verification with E language ebook. **broken link removed** ------------- Saho
  15. S

    Who can share me some vera doc, especially some introduction

    Sources?? Hello. Can you tell us where these documents are taken from? If these are the user documents supplied by the Vera, then tell us! It is useless to us. We have it installed already. Thank you. Saho
  16. S

    Who uses SynaptiCAD products

    tutorial on synapticad Hello. I would like to who ( in this forum ) uses SynaptiCAD products. I am using its TestBencher Pro to automate my VHDL testbench. However, I could not simulate the project (using the tutorial example) in ModelSIM from Testbencher Pro (version 9.0p). Am i missing...
  17. S

    Some Good EDA Vendor Presentation Stuff

    free download presentations (no points deducted!) www.cic.edu.tw/information/info_seminar/2002_design_tool_workshop/ pdf/TransEDAVN.pdf www.cic.edu.tw/information/info_seminar/2002_design_tool_workshop/ pdf/xxxxx... (you know what I meant!)
  18. S

    question regarding Synopsys VERA

    hello aramis: Do you have any document in linking Vera to Cadence Verilog (I assume it is LDV 3/4/5 on linux). Please clarify. SAHO
  19. S

    question regarding Synopsys VERA

    Vera hehe. I have some question regarding Synopsys VERA. How do I execute VERA Testbench? Do I need only software VERA 5.1.1 from Synopsys FTP in order to execute VERA coded testbench? Or, I will need to install Synopsys VCS version xx and VERA 5.1.1 software. please clarify. Does Synopsys...
  20. S

    Dump ".fsdb" in modelsim NT version?

    debussy fsdbdump You may want to take a look at the link below **broken link removed** **broken link removed** **broken link removed** SAHO

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