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  1. richloo

    [HELP] Elab error with Cadence ams(spectre) using VHDL netlist

    ncelab(64): 09.20-s016 1) by using "OSS-based netlister with irun" ERROR: Missing .cdb or .oa file in library c090_phy_lib cell c090_bias view bhv. The OSS netlister requires a .cdb or .oa file in lib/cell/view directory. If one does not exist, you can create one either by importing the...
  2. richloo

    [Help] Problem with onboard regulator

    Hey guys, I got a scenario during power down where my design still have VCCIO (3.3V) stay above my inverter's VIL level. This has translated into my chip is still power on. I have no idea on board design. Does this scenario hold true? How would the industry spec their power supply rail in term...
  3. richloo

    [Help] Ultrasim command usage

    .usim_vr Hi guys, Can anyone tell me how to use .usim_vr to speed up voltage regulator time? Thanks in advance.
  4. richloo

    [Ultrasim]How to load dc operating point

    ultrasim load dc Hey guyz, can u tell me how to load the dcOp.dc into the simulation after my first run on "save DC operating point". I found that the dcOp.dc is a binary file which I cannot use "readic" to load them. Any idea? Thanks in advance.
  5. richloo

    BSIM model design flow

    Can anyone tell me about the design flow on how the bsim model is created? Thanks in advance.
  6. richloo

    Ques on coupling effect and optimization for buffer design

    Hi guyz, We have seen coupling effect takes place everywhere in a fast switching single ended buffer circuit. Any material about how to counter the coupling effect? I am currently designing a buffer. How do we actually optimize for the coupling effect between bias generator and the pad seen by...
  7. richloo

    Need help on deglitch circuit design

    Hi guys, I am looking for deglitch circuit/topology for designing an input buffer. Can anyone suggest any reference or material on this? Btw, what is the care that i need to aware of? Thanks in advance.
  8. richloo

    Need help on real time software operation

    Hi guys, I have a test software install on a PC with winXP to test a device on IDE. However, I found that I need to set the process priority to real time using task manager, in order to get an accurate result. The problem is everytime I relaunch the test software, i need to manually reset the...
  9. richloo

    Need help on dual voltage circuit

    Hi guys, need ur help urgently. I have a buffer circuit need to be operated in either high voltage or low voltage supply. My question is, what kind of mechanism can I use to switch from one voltage supply to another? since i have 2 supply on chip. Thanks in advance.
  10. richloo

    Need help on level shifter

    Can u guyz explain the operation of the circuit shown below. Especially the cross paired pmos. Thanks in advance!
  11. richloo

    Need help to determine Q factor

    Hi there, i have designed a Butterworth low pass filter, but i don't know how to measure Q factor from simulation to comfirm my design. Can u guyz help me out? Thanks~!!!
  12. richloo

    On-chip automatic frequency tuning?

    Hi there, I am looking for this functional block. Can u guys give me some advice and material to refer to? Frequency-tuning & Q-tuning, which one is more critical for implementation whenever there is a process variation? Thanks in advance.
  13. richloo

    Need help on gm measurement

    Need help from u guyz... i have simulated a gm cell, but the problem is which point of gm should i take from the plot? i mean this is a large differential input signal, should i take at the common mode voltage which is 0.9V? i m using 1.8V single supply. input: inp= DC sweep 0->1.8V inn=0V...
  14. richloo

    What is a linear phase filter?

    Hi there, What is linear phase filter? Dose it related to the conventional filter i.e. Butterworth,Bessel,Chebychev... etc? Thanks in advance!
  15. richloo

    Low voltage wide-swing cascode current mirror

    wide-swing cascode current mirror martin Hi there, i've failed to bias wide-swing cascode current mirror properly using 1.8V supply. The circuit i used is Fig 6.11 from Ken Martin book. Is it impossible to bias 4 transistors in cascode because of 4xVdsat? I need high current so that i can reach...
  16. richloo

    Need help on analysis in Spectre

    Can anyone pls tell me the step on how to use the "stb" analysis in Spectre, to test the stablilty (gain margin,phase margin) of an opamp... I feel difficulty in finding the exact value of these margin, base on the graph generated. Thanks in advance!
  17. richloo

    Need advice on opamp design

    Hello, i am lack of experience in choosing different type of topology in opamp design. Practically, for 2 stage classical & folded cascode opamp, what is the highest gain or gain bandwidth product that they can hit? My application is high frequency filter, is it possible to use opamp-RC rather...
  18. richloo

    All layers are blackened when I open/create cell in Virtuoso

    Need help on Virtuoso Hi there, i m having trouble when i create or open a cell in Virtuoso, all layers are blackened. Others are working fine. Below is the CDS log file. Anyone there have any idea? Thanks in advance.[/img]
  19. richloo

    Looking for examples of NMOS analog microcircuits

    NMOS microcircuits Anyone who know or have some example of NMOS analog microcircuit? What is the advantage of NMOS only microcircuit compare to CMOS microcircuit? Thanks in advance.
  20. richloo

    How to measure Rout & Rin using Cadence Analog Design?

    input resistance measure breadboard Hi, i am new to cadence software. Can anyone tell me the step to measure input resistance and output resistance of a circuit? Thanks in advance!

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