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  1. Shlapenka

    Problem with printing Layout L prints file to a post script file

    Hi all, I have this problem, when i want to print to a post script file, Layout L prints file but i get not whole view of my layout. I use this printer: Hewlett-Packard DesignJet 5000PS (Postscript): \ :manufacturer=Hewlett-Packard: \ :type=postscript2: \ :maximumPages#30: \...
  2. Shlapenka

    Request for info about 45nm design rules

    Re: 45nm design rules design rules depend on your foundry, which one do you use?
  3. Shlapenka

    Digital clock design help required

    hi dani, You might refer to http://www.elec.mq.edu.au/~cl/files_pdf/elec166/lect_pt2_chap1516.pdf starting from page 16-9, there is described a digital clock made from few counters, could give you a start. Hope this helps! Good luck, Shlapenka.
  4. Shlapenka

    A question about guard rings of PNP transistors

    hi reneezl, no it is not neccessary. It is a good idea to add a n-type guard ring for PMOS transistors, this way they will be protected from horizontal currents, that may interfere with their work. Double guard ring is double protection, you surround n-type guard ring with a p-type guard ring...
  5. Shlapenka

    How to correctly ground a NMOS transistor?

    Re: nmos grounding hey alfredop, thank you for very clear answer. yes i am using a gpdk090v4. now i clearly understand, +rep for everyone!
  6. Shlapenka

    I can't find Extract_parasitic_caps section in Cadence Virtuoso 6.1.0

    Re: Parasitic caps might sound silly but where do i find QRC? not sure i have this...
  7. Shlapenka

    I can't find Extract_parasitic_caps section in Cadence Virtuoso 6.1.0

    Parasitic caps Hi everyone, When i wan to do layout extraction with parasitic caps i am having a problem. I go to Verify>Extract... Then i choose Set Switches and in there suposed to be Extract_parasitic_caps selection, but there is no such thing! Only MergePinAndNet (provided a image below)...
  8. Shlapenka

    How to correctly ground a NMOS transistor?

    Hello everyone, I am having this problem, connecting bulk connections to substrate. When its PMOS i have no problem, i make a Ntap in the same nwell as the PMOS is and connect it to VDD. When it comes to NMOS, i cant figure it out... I put a NMOS transistor, near it i put a Ptap and connect...
  9. Shlapenka

    Installing Cadence IC 5141 on Linux and Windows

    Re: cadence installation im afraid there is no cadense on windows platform, only linux. In fact im using vmware with centOS5 linux, on wich my cadence is running. You can get vmware, make a virtual machine there and according to instructions proivided above install your cadence :)
  10. Shlapenka

    Installing Cadence IC 5141 on Linux and Windows

    Re: cadence installation hi, you may wan to look to this thread : it has detailed info on installing. hope this helps!
  11. Shlapenka

    Connecting pin B of resnsppoly - N+ poly resistor with salicide

    Re: resnsppoly problem here is what i found in spectre model: ************************************************************************** * Non-Salicided P Poly Resistor ************************************************************************** inline subckt gpdk090_resnsppoly (PLUS MINUS B)...
  12. Shlapenka

    Connecting pin B of resnsppoly - N+ poly resistor with salicide

    Re: resnsppoly problem here is the info form specification: Spectre Netlist Spectre Model Name = “gpdk090_resnspoly” R1 (B MINUS PLUS) resnsppoly_pcell1 segL=8u segW=1.5u Subckt resnsppoly_pcell1 B MINUS PLUS Parameters segL=8u segW=1.5u R0 (PLUS MINUS B) gpdk090_resnsppoly l=segL w=segW Ends...
  13. Shlapenka

    Why the net In1 in this layout is incomplete?

    Re: Incomplete net yes everything is as u said here is the pic: **broken link removed** it is a picture of generated connections. Added after 35 minutes: Solved my problem! Looks like it wa problem with my ntap's. I had created them myself and it seems something was wrong with them, even...
  14. Shlapenka

    Connecting pin B of resnsppoly - N+ poly resistor with salicide

    Re: resnsppoly problem so if ive got it right, i must make like an ntap wich will be the N+ contact?
  15. Shlapenka

    Why the net In1 in this layout is incomplete?

    Re: Incomplete net it is conned to In1 pin, it is that big rectangle in top. That pin was generated from schematic as was generated all other pins and devices..
  16. Shlapenka

    Connecting pin B of resnsppoly - N+ poly resistor with salicide

    Re: resnsppoly problem im sorry i mistyped it is actualy an resnsppoly – N+ poly resistor without salicide it has these layers: Poly Pimp SiProt & Resdum (Marker Layer) Cont Metal1 and is placed on substrate.
  17. Shlapenka

    Why the net In1 in this layout is incomplete?

    Re: Incomplete net In schematic it was named In1 automaticly, in layout it was also named in1 after connecting transistors, ntap and In1 pin. (text in green in layout pic is added by me, it is not shown in layout i added it with MS paint). Pin was metal1 layer, connections to it are made by...
  18. Shlapenka

    Why the net In1 in this layout is incomplete?

    Incomplete net Hi all, So here is my problem: i designed a circuit and now doing a layout. The layout is complete, has no DRC errors but there is a problem. In Fig.1 i am showing the part of layout that has a input In1, ant it is connected to PMOS transistors trough net named In1 (bright white...
  19. Shlapenka

    Connecting pin B of resnsppoly - N+ poly resistor with salicide

    resnsppoly problem Greetings all, Here is my problem: in my design i use resnsppoly – N+ poly resistor with salicide, it has 3 pins - PLUS, MINUS and B (picture No.1). I connected it as is shown in picture No.2, the B pin to ground. In layout mode resistor is as shown in picture No.3. Its pins...
  20. Shlapenka

    need help with Cadence IC6.1.0

    thank you wpchan05, will get pdk for 6.1 :)

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