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I have this problem, when i want to print to a post script file, Layout L prints file but i get not whole view of my layout.
I use this printer:
Hewlett-Packard DesignJet 5000PS (Postscript): \
When i wan to do layout extraction with parasitic caps i am having a problem.
I go to Verify>Extract... Then i choose Set Switches and in there suposed to be Extract_parasitic_caps selection, but there is no such thing! Only MergePinAndNet (provided a image below)...
I am having this problem, connecting bulk connections to substrate. When its PMOS i have no problem, i make a Ntap in the same nwell as the PMOS is and connect it to VDD. When it comes to NMOS, i cant figure it out... I put a NMOS transistor, near it i put a Ptap and connect...
So here is my problem: i designed a circuit and now doing a layout. The layout is complete, has no DRC errors but there is a problem. In Fig.1 i am showing the part of layout that has a input In1, ant it is connected to PMOS transistors trough net named In1 (bright white...
Here is my problem: in my design i use resnsppoly – N+ poly resistor with salicide, it has 3 pins - PLUS, MINUS and B (picture No.1). I connected it as is shown in picture No.2, the B pin to ground. In layout mode resistor is as shown in picture No.3. Its pins...
So here is the problem, i found alot of tutorials for previous versions of IC, but cant find any for IC6.1. I am makinig an CMOS inverter, everything goes well until i reach state where in previous versions it was deign generated from source (in Virtuoso XL Layout editor: Design>Generate from...
So here is the problem, i found alot of tutorials for previous versions of IC, but cant find any for IC6.1. I am makinig an CMOS inverter, everything goes well until i reach state where in previous versions it was deign generated from source (in Virtuoso XL Layout editor...
I need some info, pdf's or anything you can help me with about 90nm technology process. Comparison to other technologies, anything you have please post it, will be very thankful!
Hello everyone :)
Here's my problem: I am making a low-voltage CMOS negative impedance converter for analogue filter applications.
here is the scheme: **broken link removed**
I made transistors with these 0.35 um models ...
90 nm topology rules
I am looking for 90 nanometer topology (layout) rules. I meen rules for designing a 90 nanometer based IC. Can anyone link some articles? Been searching for few hours now, couldnt find anything decent... Thank you.