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    relacing 5V TTL tolerant FPGA with 3.3V TTL I/O tolerant FP

    Hi We used old spartan device which was 5V I/O tolerant. That device is obsolete one.Now, we are going to replace with new FPGA (SPARTAN3 series).But,these devices which are now in market are 3.3V tolerant only.How to face this problem? Please suggest me. regards, Balu
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    AMBA AHB Arbiter Test Environment

    Hi. I need a Processor BFM for our test environment to verify our AMBA AHB system. Please I need suggesion. Can I get free BFM's for any processors to test our environment. Basically, We need processor BFM which can work like a MASTER and to configure our ARBITER. Any inputs are welcome!
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    BFM Bus Functional Model

    Hi I am looking for a BFM for simple,generic processor.I am very much new for writing BFM.Any inputs are welcome.Actually, whether BFM can be written systemverilog also.What is the preferred choice?We have our designs in systemverilog.I want to see the example codes for BFM for any module.
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    Suggest me a free/evaluation version ASIC design tools

    Hi I am new to digital design tools. Can anybody suggest free/evaluation version asic design tools which can be downloaded or requested? Thanks in advance.
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    Mealy vs Moore Design

    convert mealy machine to moore machine This following explanation is for tronix... As I previously said,u should have tried on ur own by solving a simple sequence detector.it's ok... now we take a sequence detector which whas to detect bit sequence of 101... ok... Let me say..... already it has...
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    Mealy vs Moore Design

    difference between moore and mealy Hi guys! Please go through any text book covering both machines. thing is.... Whether it is mealy or moore,next state depends on both input a well as present state. only the difference is Output where u will take. ...in mealy,output depends on present input as...
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    good vlsi institutes in bangalore

    vlsi course 1)Indian Institute of science---ofcourse as it is a govt organisation,u need to follow certain interviews and show better performance. 2)MS ramaiah college. 3)Tejas Design centre also offers you a course which will enable you to get vlsi career.
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    Which gates act as universal gates?

    Re: Universal Gates I already mentioned all possible universal gates in this post. XOR is not an universal gate.can u form NAND gate or NOR gate with using only XOR gate...?try...u can't.so XOR is not an universal gate.If u can form NAND gate(which is an universal gate) using XOR gate,then...
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    Which gates act as universal gates?

    Re: Universal Gates-Mux,Inhibit,implication,HA etc. Universal gates are those from which we can produce all kind of gates. following are the examples. 1)And-Or-Not 2)NAND 3)INHIBIT X.Y' X'Y 4)iMPLICATION X+Y' X'+Y 5)NOR 6)XOR WITH AND 7)EQUALITY(XNOR)...
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    Suggest me some books about CAD algorithms for VLSI

    i want to learn CAD algorithms to enable layout of analog,rf,mixed signal,SOC'S. I WANT TO LEARN CAD algorithm development for VLSI. can anybody suggest any good books,web sites,course notes,etc.... thanking u.
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    urgent help needed reg cadence

    hi i am doing layout in tanner Ledit.in a few days,we may get cadence licences. so,is there any possibility of exporting tanner ledit to cadence layout.? pls tell me urgently. and i also want to know other free RF Layout tools. thanks in advance.
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    Books on VLSI Back-end

    hi can anybody pls suggest me good,basic books for VLSI back -end design. thanks.
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    pss analysis for LNA in cadence

    i am posting one document.it may help u to find all characteristics reg LNA.if not tell me,i amy post few more docukments.....ok....
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    pss analysis for LNA in cadence

    hi i designed a circuit for LNA.i simulated for s parameters.i wanted to do pss analysis to find out 1 db compression point and iip3.i am getting problems by setting the analysis(specifying the parameters in the analysis window).can anybody help in this regard..or post any help material...
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    lna noise figure,s parameters in cadence

    cadence noise figure simulation hi we r having cadence licences and that too version 5.0.0.so we have spectre rf simulation facility.the problem is ...as we r in the institute, we r not able to see online documentation . regarding ....finding out s parameters,we have to specify the ports.let...
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    lna noise figure,s parameters in cadence

    s parameter+lna hi i am doing LNA for 2.4G wireless lan application.i am struggling to characterise regarding noise figure,s parameters in cadence.can anubody help me to simulate the circuit for those parameters in cadence.i want detailed information.pls post some documents or help manual...
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    how to simulate to get NOISE FIGURE....

    hi BRM my qn is how to simulate to calculate the noise figure and linerity. THANX 4 UR REPLY.
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    how to simulate to get NOISE FIGURE....

    pls help me how to calculate NF of my LNA ckt.
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    microwave and RF handbook

    can anybody uoload "microwave and RF handbook" CRC press,2001. somebody told it is a good book for RF designers. pls upload ......
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    design of rf transceiver for wifi

    hi all i am going to work on project"design of rf transceiver for wi-fi(802.11B). can anybody help me by posting the links related to the literaure of project like thesis,old project,journal papers,rf course etc. i also want to learn the inticacies of analog layout. pls help me out.

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