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  1. R

    Generating base audio clocks with Spartan 6 (PLL?)

    I have a Spartan 6 clocked with 100 MHz (Atlys) and I want to generate the base audio clocks 22.5792 MHz and 24.576 MHz (or some multiple of them). For Fclk/3125 = Fvco/768 I would get Fvco = 24.576 MHz, but this would mean the PLL frequency is 32 KHz. Reading the specs this seems a much to low...
  2. R

    DC link voltage for 3-phase inverter

    Hi, I aim to build a 3-phase inverter (PWM) with output 3x230VAC (Y, 3x400VAC Delta), but I'm confused as to how calculate which DC link voltage is needed for the required outputs ? TIA /R
  3. R

    Depth of pipelining (Spartan 6)

    Hi all, I'm setting up a synth engine and I thought I'd pipeline it so I can get high voice count throughput, however, I'm estimating (very roughly) that I'll get somewhere between 30 to 50 pipeline stages. Is this "off the chart" when it comes to pipelining, or is it within reasonable bounds ...
  4. R

    Question on TDM (Spartan-6)

    I'm planning on doing a VHDL synth implementation on an Atlys board (Spartan-6), and I have a conceptual question regarding TDM. Since I hope to have ample room (timewise) I plan on supply a HW synth voice engine with structs (or records) of parameters that the engine should process in a TDM...

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