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    Bidirectional memory to non verilog

    I have a module for a bidirectional memory but I need to get it working with non-bidirectional lines. I'm thinking this is simple but I'm stuck. Here's the module module ram16x4( input [3:0] address, inout [3:0] data, input ce, we, oe ); reg [0:15] [3:0] memory; //16 x 4 RAM assign data =...
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    Pipeline Register Data Path

    I'm in need of a bit help regarding pipelining in verilog. I have a register module with enable and asynchronous reset and what I'm trying to do is create a structural model of the first stage. I have coded the register module already but I'm a little stumped on how to start the first part of...
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    Memory Design Help Verilog

    I'm quite new to verilog and don't quite understand things that well yet so I apologize if this is a simple question but I'm having a difficult time putting my design into verilog. It's a 64x8 Memory Unit that's suppose to be designed with a 16x4 SRAM. I think I have the decoder module and 16x4...
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    Verilog Memory Design

    I already have drawn out the block diagrams and SRAM and SIMMs but I always have a very difficult time with verilog. Can anyone help me or show me a good example that I could base it off of? I looked but couldn't find many useful information. This is designing a 64x8 memory unit with using 16x4...
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    [SOLVED] FSM Verilog help with output

    I'm suppose to do a finite state machine and I'm still fairly new with verilog so if anyone can look over my code to see why it's not working correctly that'll be great. I have my test bench already and it seems to be working correctly but the outputs are all wrong. It doesn't seem to output...
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    8 Bit ALU Verilog Code

    I have a very difficult time understanding verilog and programming on it. Is there anyone that can help me with 8 bit ALU Module code or at least how to understand this better? We're also suppose to design a 8 bit 4 to 1 mux and 8 bit 2 to 1 mux. I think I figured out the 2 to 1 mux but what I'm...

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