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in a CMOS circuit, what is meant by drive strength ? For example in TSMC cell library there are cells labeled AOI221X1 AOI221X2 etc. What is the significance of X1, X2 etc. Kindly give me a detailed reply by stating the defenition of drive strenth, signaifcance and factors affecting drive...
I am using fc4 and suddenly all desktop settings changed and all my control panel setting changed. Now I am unable to bring workspace switcher in to control panel. Kindly help me to solve this.
For given large combinational or sequentail gate level circuit, how can I calculate total switching transitions (0->1 and 1->0) provided that two input vectors in sequence.
Kindly suggest one efficient idea so that I can implement it effectively
I have installed beamer class as root and class fiel are stored in the directory
/usr/share/texmf/tex/latex/beamer/base. But while I am trying to run one simple tex program it is showing error as shown below.
ash-3.00$ latex test.tex
This is TeX, Version 3.14159 (Web2C 7.4.5)
I have a basic doubt in gate delays. When we analyze the gate delay of and gate in 90nm , 65nm and 45nm technology which one is more. Pl. give me proper exlanation and justification for the same
delay in 90 nm
How can I calculate typical basic gate delay for 90nm and 45 nm technology.
Can anyone suggest materail or approaches for the same. My aim is to calculate a encoder circuit delay in 90nm and 45nm technology implemenattion.
Pl. help me