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1) I can generate VHDL/Verilog Code.
2) I can't provide during generation process, needed parameters. Just can't change any fields you see in Core-Generator. The only thing I can do, during generation process is typing "next,next,next" :(
I have newbie question about Xilinx Core Generator: FIR-compiler.
When I start the core ( FIR-compiler ) , and try to customize its parameters, I can change nothing. Just can't select anything except entity name, and provide name of coe file.
I tried do the same in another computers...