Welcome to our site! EDAboard.com is an international Electronics Discussion Forum focused on EDA software, circuits, schematics, books, theory, papers, asic, pld, 8051, DSP, Network, RF, Analog Design, PCB, Service Manuals... and a whole lot more! To participate you need to register. Registration is free. Click here to register now.
You can find manual by synopsys' application engineer.
Others you should understand basically theory about PrimeTime, then you can write some tcl file about PrimeTime for your circuit and analyse timing of your circuit base on your tcl file. If you think that timing is not...
If let your circuit must meet timing and function of timing after P&R, you have better do clock tree synthesis. It was done by CTS tool.
logic synthesis is process that translate RTL description to gate netlist.
Re: Routing Power
Because you should think every gate can work under certain voltage, The same, we shouldn't think that IR is affect work of circuit and try to small IR. Power should routing on top met.
The tools of synopsys and the cadence aren't get timing library, timing library can only get from the manufactory. STA and PrimTime are only used as anaysis timing of circuit, it can't get timing library.