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  1. M

    problem of IC5.0 installed on Redhat 7.2

    I have meet this question. I hope that the daxia give some advice. Thanks.
  2. M

    Need PrimeTime manual

    primetime manual You can find manual by synopsys' application engineer. Others you should understand basically theory about PrimeTime, then you can write some tcl file about PrimeTime for your circuit and analyse timing of your circuit base on your tcl file. If you think that timing is not...
  3. M

    How to model #delays in RTL?

    Re: #delays in RTL This is no delay in RTL. you can add somes buffer in circuit if you wish some delay during synthesis.
  4. M

    Why do we need to check the hold violations before setup?

    Re: Help on hold check Yes. I agree jarodz's viewpoint. We must analyse setup/hold time in IC design.
  5. M

    What are the tools used in the ASIC design flow?

    Re: asic flow asic flow : RTL simulation ---> RTL synthesis ---> P&R tools: RTL simulation : cadence's NC-sim or synopsys' VCS etc RTL synthesis : synopsys' DC P&R: candence's SE or avanti's apollo or astro etc others: CTS , Prime Time etc
  6. M

    Is dualport ram much more costly than singleport ram asic?

    bitcell size for single and dual port sram OKay. But when you select dualport ram or singleport ram, you should be base on your circuit in fact. i.e speed of circuit and data throughput etc
  7. M

    clock tree synthesis versus logic synthesis

    If let your circuit must meet timing and function of timing after P&R, you have better do clock tree synthesis. It was done by CTS tool. logic synthesis is process that translate RTL description to gate netlist.
  8. M

    How to extract SPICE netlist from GDS file

    does pspice accept gds files ? You can run LPE(in fact it is LVS) while you think from GDS netlist to SPICE netlist. But you should add some parameter in you .lpe file. i.e. cap, res etc.
  9. M

    Where can I get the "HDL Chip Design" book by Smith?

    Re: HDL Chip Design book Hi, omid219. Can you sent "hdl chip" to my email. thanks. email: wxsilence@yahoo.com.cn
  10. M

    synthesis script needed

    you can find some script language for example tcl. you can find it in synopsys' dc tool.
  11. M

    help needed in getting started in ASIC

    You should study some books about Logic design ,layout design,verify etc. The same you should study some tools of IC design.
  12. M

    what is Hercules Bundle (DRC/LVS/ERC/MW)

    erc lvs drc DRC: Design Rule Check, example W/L check and distance of bewteen Metal etc. LVS: Logic verify Schematic ERC: Electric rule check
  13. M

    Looking for useful books/websites about physical design

    Re: about physical design Thers are some books you can look: 1 IC design 2 IC Mask design 3 The Art of Analog Layout 4 CMOS Circuit Design,Layout,and Simulation
  14. M

    Where can I find some tutorial about tcl?

    you can enter into websit: https://www.tcl.tk There should have some tutorial about tcl.
  15. M

    Schematic Simulation with Verilog XL

    You can reset or set. you can add default to q and qn in testbench file also.
  16. M

    VCS, NC-Verilog and Modelsim, which is the best simulator??

    Re: VCS, NC-Verilog and Modelsim, which is the best simulato I use NC-verilog. It is the best simulation.
  17. M

    mostly used verification language in industries?

    I use verilog mostly. It's no important that you use the sort of verification language, I think that you like that verification language.
  18. M

    Which metal layer is suitable for power routing around chip?

    Re: Routing Power Because you should think every gate can work under certain voltage, The same, we shouldn't think that IR is affect work of circuit and try to small IR. Power should routing on top met.
  19. M

    Any tool to get timing library

    The tools of synopsys and the cadence aren't get timing library, timing library can only get from the manufactory. STA and PrimTime are only used as anaysis timing of circuit, it can't get timing library.

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