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  1. J

    Resuming simulation from CLI mode in VCS

    Dear Friends, I am running VCS to dump fsdb files. The number of fsdb files are large in number, which are bit difficult to handle them at a time because each of the file require some GB of spaces. So, its really impossible to dump all the files at a time. I thought of handling this problem...
  2. J

    Extra pattern on top of the existing pattern set

    Hi friends, I have one small query. I hope you might be wel aware that to increase the fault coverage, in some cases it is required to add some extra patterns on the top of the currently available patterns. I wanted to know, when these patterns are available during the scan desing cycle...
  3. J

    scan reordering and scan stitching

    Hi frnds, This post is regarding the difference between the scan reordering and scan stitching. I came across the book "The VLSI test principle..." by Xioqing Wen et al. where they have defined the Scan stitching methodology as the final connection between the scan cells, the out put of...
  4. J

    Scan optimization: is it during scan insertion or ....

    Hi DFTian, I am bit doubtful about the scan optimization ( constraint: power, area), exactly when it is done, is it during scan insertion that is done with DFTCompiler or it has to do with Astro (synopsys tool for scan optimization and ....). Please give your healthy reply...
  5. J

    Design Compiler warning OPT-1206

    opt-1206 Hi designerAll, Can any one suggest me how to avoid the warning OPT-1206 in design compiler. The OPT-1206 defination is: " The register Ro is constant and will be removed ". This warns that some of the flipflop from my design are getting removed as a result...
  6. J

    Flops with CONSTANT value is not synthesized as Scan Flop..

    Hi DFTer, Does the flowing warning affect the functionality of design ? Information: The register 'P2/P1/InstQueueRd_Addr_reg[4]' is a constant and will be removed. (OPT-1206) How do I modify my design to avoid the removal of Flops...
  7. J

    TetraMax DRC violation

    tetramax violations Hi All TetraMax Users, Please Help Me ! The error I am getting while during the DRC checking is following : " Wire gate (12) failed contention ability check for drivers 469 and 465. (Z3-1)" I am not able to troubleshoot this error. I...
  8. J

    LSI library for design synthesis

    Hi friends, Can any one please share the experience of using the library " lsi_10k " . For me, I faced some problem because of the unavailability of source file(.v or .vhd file) . In wait for yours replies, JAY.......
  9. J

    source file for lsi library

    Hi frnds, If some one have tried using lsi_10k or other lsi libraries in synthesinzing design using synosys DC he might have faced the problem either dring the time of simulation using VCS or may be during the time of test pattern generation using TetraMax. I am facing the...
  10. J

    Can VCS take a verilog netlist as input

    Hi frnd, Just I want to know that can VCS takes verilog netlist as input ? I am trying simulating a verilog netlist having scan flipflop within it. But in compile time only it is generating some error msg " instances with unresolved module " this is because, in the netlist file...
  11. J

    synthesizing using only nand nor and not gate

    Dear frnd , can any one help me out in synthesizing a ckt using only nand nor and not gate. i am using desing vision tool for logic synthesis. "Keep posting in forum and enhance your output...................." Jaynarayan...
  12. J

    Converting EDIF file to verilog

    Hi frnd, Have ne 1 came across this kind of problem where it is required to convert an EDIF file to verilog or VHDL . I need favour in this. PLease post some help. " FastScan is better than TetraMax " Jaynarayan......... Bangalore, India.

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